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Thread-Index: AQHTr+rjfml7TUbxHUe+4LwAlvCYuQ== Date: Tue, 27 Feb 2018 16:49:09 +0000 Message-ID: References: <20180227164853.3512-1-Marvin.Haeuser@outlook.com> In-Reply-To: <20180227164853.3512-1-Marvin.Haeuser@outlook.com> Accept-Language: de-DE, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-incomingtopheadermarker: OriginalChecksum:C12906D9D9FE3437A451BEA939B724AC1840966B18B0CE43D5F8CB8588C44E20; UpperCasedChecksum:FB9B56E235AEFA5C01910B435DE3AC693BCF945D6159E42CD891FC4AB8C48476; SizeAsReceived:7213; Count:47 x-ms-exchange-messagesentrepresentingtype: 1 x-tmn: [mPuACzEhV8z5uk0LmtzaaULQsBcIUjDS] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; VE1EUR02HT021; 6:mGf9VCeGgDCDbrhjGxVOwcWlevRS2vDU+k/ZN1tqOXnvw7XBMPIm9znuxfjdhQA3LLR0aG9FGdZo//MrC4M3dutZ2ALQre8ui3V5eMUZPc4FRLnzefN/sykB2LQhiV15yMzlRUx+XWx6jR/KccZJVXdGBQXkYyS2uqV2SyjB0z6sqmYX8vaefojH+1egEiS7Ipa6kLrQRR/EaPPER5eApNZOQVSajCRKLA+SCDsLa/laLE6DQuL3xMsWEwSlwYPT5o9zdcMLE5mnL5u7mOASQa8GtsE3tItpgIAkmjbW0XbCr4V/xdtwtLasVXjRTglVhCcDQbc8vZ/43GMY3NykSxEF2S4yXAITTD3uuMX4PC4=; 5:m+fKJrgU1ju9/d1jxTvwfz4t4+kcAFLvYcT+QBMiuRp+H2fJkrSxBGDb9Qc95oFsHJEkqQB7OIuY0rJ8Vc2PyM6m5aQN0kDFx9OxHQPAg09xy8xacq3L7Vj6zfa99pxbJzQdbXeJG+sSV4R/SvZ2HgDobtLK5wlKtsFXURUdqdM=; 24:iZroPAvyhTM8Fz5WfSTtyjhB+BxbLVTArK5/4n0+e1w0jh5MznCXPtWbLF4HTrBt9g8StQi9hdMqLLA0E3dZSBLLoqMD869fcGrlaIEwWbA=; 7:PC0fMJd94By3EjOrNkPuI0dGwPI9on2rY1UylcVFgJuzLc2NmaDxWj7dVKOF9YPQMrlwVi2YIKFUvcDrr+HXheRb5OMrcfnPbydgriFjvJ05JoCciUPvTyUUsSJMvRAJu7J/W9MYBq4vasyJsLimU/yumn3vre4L7BwNQbyrWHsuNm96OKPj+kme98ZJiCsQeAwcmWxUsXXunCbbRr73yjD/sPBkxrsKxffW51Y84jUM7jLENNmJTGWCQgWLqCvT x-incomingheadercount: 47 x-eopattributedmessage: 0 x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(201702061078)(5061506573)(5061507331)(1603103135)(2017031320274)(2017031324274)(2017031323274)(2017031322404)(1603101448)(1601125374)(1701031045); SRVR:VE1EUR02HT021; x-ms-traffictypediagnostic: VE1EUR02HT021: x-ms-office365-filtering-correlation-id: ca8c67f3-1e82-43f5-2975-08d57e020554 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(444000031); SRVR:VE1EUR02HT021; BCL:0; PCL:0; RULEID:; SRVR:VE1EUR02HT021; x-forefront-prvs: 05961EBAFC x-forefront-antispam-report: SFV:NSPM; SFS:(7070007)(98901004); DIR:OUT; SFP:1901; SCL:1; SRVR:VE1EUR02HT021; H:AM4PR06MB1491.eurprd06.prod.outlook.com; FPR:; SPF:None; LANG:; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ca8c67f3-1e82-43f5-2975-08d57e020554 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Feb 2018 16:49:09.3635 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1EUR02HT021 Subject: [PATCH 2/5] MdePkg/SPI: Add missing definitions. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Feb 2018 16:43:07 -0000 Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable The PI Specification lack a bunch of definitions required to implement the protocol stack. Add definitions with bit values, ordered in the same way as in the specification. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser --- MdePkg/Include/Protocol/SpiConfiguration.h | 15 +++++++ MdePkg/Include/Protocol/SpiHc.h | 47 ++++++++++++++++++++ MdePkg/Include/Protocol/SpiIo.h | 23 ++++++++++ 3 files changed, 85 insertions(+) diff --git a/MdePkg/Include/Protocol/SpiConfiguration.h b/MdePkg/Include/Pr= otocol/SpiConfiguration.h index c36a809f4232..9d6c1e94d12b 100644 --- a/MdePkg/Include/Protocol/SpiConfiguration.h +++ b/MdePkg/Include/Protocol/SpiConfiguration.h @@ -178,6 +178,21 @@ typedef struct _EFI_SPI_BUS { VOID *ClockParameter; } EFI_SPI_BUS; =20 +// +// SPI Peripheral attributes. +// Note: The UEFI PI 1.6 specification does not specify values for defines +// below. The order matches the specification. +// + +/// +/// The SPI peripheral is wired to support a 2-bit data bus +/// +#define SPI_PART_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT0 +/// +/// The SPI peripheral is wired to support a 4-bit data bus +/// +#define SPI_PART_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT1 + /// /// The EFI_SPI_PERIPHERAL data structure describes how a specific block o= f /// logic which is connected to the SPI bus. This data structure also sele= cts diff --git a/MdePkg/Include/Protocol/SpiHc.h b/MdePkg/Include/Protocol/SpiH= c.h index 71c75431e4e8..dabbc9ae231d 100644 --- a/MdePkg/Include/Protocol/SpiHc.h +++ b/MdePkg/Include/Protocol/SpiHc.h @@ -35,6 +35,53 @@ =20 typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL; =20 +// +// SPI Host Controller Attributes. +// Note: The UEFI PI 1.6 specification does not specify values for defines +// below. The order matches the specification. +// + +/// +/// The SPI Host Controller supports write-only operations. +/// +#define HC_SUPPORTS_WRITE_ONLY_OPERATIONS BIT0 +/// +/// The SPI Host Controller supports read-only operations. +/// +#define HC_SUPPORTS_READ_ONLY_OPERATIONS BIT1 +/// +/// The SPI Host Controller supports write-then-read operations. +/// +#define HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS BIT2 +/// +/// The SPI host controller requires the transmit frame to be in most +/// significant bits instead of least significant bits. The host driver w= ill +/// adjust the frames if necessary. +/// +#define HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS BIT3 +/// +/// The SPI host controller places the receive frame to be in most signifi= cant +/// bits instead of least significant bits. The host driver will adjust t= he +/// frames to be in the least significant bits if necessary. +/// +#define HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS BIT4 +/// +/// The SPI controller supports a 2-bit data bus. +/// +#define HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT5 +/// +/// The SPI controller supports a 4-bit data bus. +/// +#define HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT6 +/// +/// Transfer size includes the opcode byte. +/// +#define HC_TRANSFER_SIZE_INCLUDES_OPCODE BIT7 +/// +/// Transfer size includes the 3 address bytes. +/// +#define HC_TRANSFER_SIZE_INCLUDES_ADDRESS BIT8 + /** Assert or deassert the SPI chip select. =20 diff --git a/MdePkg/Include/Protocol/SpiIo.h b/MdePkg/Include/Protocol/SpiI= o.h index 8c5d96bb04b2..92659122a37e 100644 --- a/MdePkg/Include/Protocol/SpiIo.h +++ b/MdePkg/Include/Protocol/SpiIo.h @@ -56,6 +56,29 @@ typedef enum { SPI_TRANSACTION_WRITE_THEN_READ } EFI_SPI_TRANSACTION_TYPE; =20 +// +// SPI IO Attributes. +// Note: The UEFI PI 1.6 specification does not specify values for defines +// below. The order matches the specification. +// + +/// +/// The SPI host and peripheral supports a 2-bit data bus +/// +#define SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT0 +/// +/// The SPI host and peripheral supports a 4-bit data bus +/// +#define SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT1 +/// +/// Transfer size includes the opcode byte +/// +#define SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE BIT2 +/// +/// Transfer size includes the 3 address bytes +/// +#define SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS BIT3 + /** Initiate a SPI transaction between the host and a SPI peripheral. =20 --=20 2.16.0.windows.2