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From: Marvin H?user <Marvin.Haeuser@outlook.com>
To: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: Rafael Machado <rafaelrodrigues.machado@gmail.com>
Subject: Re: Sec and Reset vector
Date: Sat, 22 Oct 2016 17:03:41 +0000	[thread overview]
Message-ID: <AM5PR0601MB25791A2B1906958CC395D64A80D70@AM5PR0601MB2579.eurprd06.prod.outlook.com> (raw)
In-Reply-To: <CACgnt78v37DqtJ-QYv=sc8XkhNN96XicnUOj7f9=ixbOpoKyqQ@mail.gmail.com>

Hey Rafael,

There actually is some generic SEC code in UefiCpuPkg you might want to take a look at. It's generic because it does not have "Intel NDA" code, such as CAR (Cache-As-RAM) etc.
The Reset Vector may or may not be part of SecCore. It's either embedded within the SecCore module, or a separate file in the FFS. You can check the start/end address of the modules (e.g. with UEFITool) and find the Reset Vector file that way.

PS.: Seems like inline images are not supported by the mailing list (or is it my error?). Either way, I do not see the image in my mail client (Outlook 2016).

Regards,
Marvin.

> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Rafael Machado
> Sent: Saturday, October 22, 2016 6:28 PM
> To: edk2-devel@lists.01.org
> Subject: [edk2] Sec and Reset vector
> 
> Hi eveyrone
> 
> I'm doing some studies on edk2 and coreboot, but I'm having some questions
> that I believe you can help.
> 
> On the journey to try to understand things since the beginning, so they make
> sense in future, I'm trying to understand how does the Initial phases of UEFI
> / PI firmware work. To do that I got a bios image and start to reverse it to
> check the modules and everything present at that bios. Now I understand, at
> least the basics, about DXE and PEI phase.
> 
> The main question that I have now is about the SEC phase.
> To try to understand the SEC phase I tried to reverse this firmware so I could
> check the reset vector's first jump or something like that.
> The surprise I have is that I was not able to find this code.
> 
> To be sure I was reversing on the correct way I generated a coreboot image.
> On the image below we can see the initial code of a firmware generated
> using coreboot
> 
> [image: pasted1]
> 
> But at the UEFI firmware I'm studying I'm not able to find anything similar to
> that.
> My guess before starting this was that at least the SEC initial code should be
> similar to the legacy way of doing things, a jmp at 0xfff:fff0 and after that the
> magic should get started with all uefi phases.
> 
> Could someone please give me some light on that?
> 
> 
> Thanks and Regards
> Rafael R. Machado
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel


  reply	other threads:[~2016-10-22 17:03 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-22 16:28 Sec and Reset vector Rafael Machado
2016-10-22 17:03 ` Marvin H?user [this message]
2016-10-22 18:19   ` Andrew Fish
2016-11-04 17:48     ` Rafael Machado
2016-11-04 17:50       ` Rafael Machado
2016-11-04 18:50       ` Andrew Fish
2016-11-04 19:33         ` Rafael Machado
2016-11-04 19:59           ` Laszlo Ersek
2016-11-04 21:18             ` Andrew Fish
2016-11-04 21:28           ` Kinney, Michael D
2016-11-04 22:19             ` Rafael Machado
2017-03-29 19:05               ` Rafael Machado

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