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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2021 14:13:31.3333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc86b2dd-49d7-460b-7127-08d90598cee8 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT031.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR08MB5817 Content-Language: en-GB Content-Type: multipart/alternative; boundary="_000_AM6PR08MB3784BDEF3E7DB1E6885510F484469AM6PR08MB3784eurp_" --_000_AM6PR08MB3784BDEF3E7DB1E6885510F484469AM6PR08MB3784eurp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Jianyong, You need to check if you're subscribed to the EDK II development mailing li= st. Otherwise, your patch email will get rejected. You can subscribe here: = https://edk2.groups.io/g/devel. Make sure that you reply to the email with subscription confirmation sent f= rom noreply@groups.io. Unless you do it, you won'= t become a member of the mailing list. I would also recommend that you wait for a day after confirming, as I belie= ve the edk2.groups.io admin will need to approve your membership. Regards, Sami Mujawar From: Laszlo Ersek Date: Thursday, 22 April 2021 at 14:57 To: Jianyong Wu , edk2-devel-groups-io Cc: Justin He , Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: Re: [PATCH v1 1/4] ArmVirtPkg: Library: Memory initialization for = Cloud Hypervisor Hi Jianyong, On 04/22/21 10:24, Jianyong Wu wrote: > Cloud Hypervisor is kvm based VMM implemented in rust. > > This library populates the system memory map for the > Cloud Hypervisor virtual platform. > > Cc: Laszlo Ersek > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Signed-off-by: Jianyong Wu > --- > ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib.inf |= 47 +++++++++ > ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoLib.c |= 94 ++++++++++++++++++ > ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLibConstructor.c |= 100 ++++++++++++++++++++ > 3 files changed, 241 insertions(+) let's sort out the meta-problems first: (1) you need a Feature Request BZ for this; . The commit messages should reference the specific bugzilla ticket URL. (2) "Clh" is a catastrophically bad abbreviation. The whole point of your work is to add Cloud Hypervisor support, so why trash the most relevant information in the file names with an inane abbreviation? (Not to mention that the name "Cloud Hypervisor" itself is as nondescript as possible. :/) (3) I have not received a cover letter (0/4). Not sure if you sent one. (4) I don't see the messages in my edk2-devel folder, or in the mailing list archives, or in the messages held for moderation at the groups.io WebUI. (5) "Cloud Hypervisor" is not something that I can justifiably spend much time on. I'm willing to review this series at the level at which I've reviewed (for example) XenPVH or Bhyve in the past, mainly focusing on style and potential regressions. However, that's not enough for the long term: someone from ARM (or elsewhere) will have to step up for permanent reviewership. Please add a patch for extending "Maintainers.txt" appropriately. Example subsystems: - ArmVirtPkg: modules used on Xen - ArmVirtPkg: Kvmtool emulated platform support - OvmfPkg: bhyve-related modules - OvmfPkg: Xen-related modules Please keep the subsystem titles alphabetically sorted in the file. Please resend. (I'm posting these comments at once because they are understandable to the community even in the absence of your patches on the list.) Thanks Laszlo > > diff --git a/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib.in= f b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib.inf > new file mode 100644 > index 000000000000..04cb1f2a581a > --- /dev/null > +++ b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib.inf > @@ -0,0 +1,47 @@ > +#/* @file > +# > +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. > +# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#*/ > + > +[Defines] > + INF_VERSION =3D 0x0001001A > + BASE_NAME =3D ClhVirtMemInfoPeiLib > + FILE_GUID =3D 3E29D940-0591-EE6A-CAD4-223A9CF55E7= 5 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D ArmVirtMemInfoLib|PEIM > + CONSTRUCTOR =3D ClhVirtMemInfoPeiLibConstructor > + > +[Sources] > + ClhVirtMemInfoLib.c > + ClhVirtMemInfoPeiLibConstructor.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmVirtPkg/ArmVirtPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + ArmLib > + BaseMemoryLib > + DebugLib > + FdtLib > + PcdLib > + MemoryAllocationLib > + > +[Pcd] > + gArmTokenSpaceGuid.PcdFdBaseAddress > + gArmTokenSpaceGuid.PcdFvBaseAddress > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdFdSize > + gArmTokenSpaceGuid.PcdFvSize > + gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress > diff --git a/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoLib.c b/A= rmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoLib.c > new file mode 100644 > index 000000000000..829d7d7aa259 > --- /dev/null > +++ b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoLib.c > @@ -0,0 +1,94 @@ > +/** @file > + > + Copyright (c) 2014-2017, Linaro Limited. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > + > +// Number of Virtual Memory Map Descriptors > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5 > + > +// > +// mach-virt's core peripherals such as the UART, the GIC and the RTC ar= e > +// all mapped in the 'miscellaneous device I/O' region, which we just ma= p > +// in its entirety rather than device by device. Note that it does not > +// cover any of the NOR flash banks or PCI resource windows. > +// > +#define MACH_VIRT_PERIPH_BASE 0x08000000 > +#define MACH_VIRT_PERIPH_SIZE SIZE_128MB > + > +// > +// in cloud-hypervisor, 0x0 ~ 0x8000000 is reserved as normal memory for= UEFI > +// > +#define CLH_UEFI_MEM_BASE 0x0 > +#define CLH_UEFI_MEM_SIZE 0x08000000 > + > +/** > + Return the Virtual Memory Map of your platform > + > + This Virtual Memory Map is used by MemoryInitPei Module to initialize = the MMU > + on your platform. > + > + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTO= R > + describing a Physical-to-Virtual Mem= ory > + mapping. This array must be ended by= a > + zero-filled entry. The allocated mem= ory > + will not be freed. > + > +**/ > +VOID > +ArmVirtGetMemoryMap ( > + OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > + ) > +{ > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + > + ASSERT (VirtualMemoryMap !=3D NULL); > + > + VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIP= TOR) * > + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)= ; > + > + if (VirtualMemoryTable =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTIO= N__)); > + return; > + } > + > + // System DRAM > + VirtualMemoryTable[0].PhysicalBase =3D PcdGet64 (PcdSystemMemoryBase); > + VirtualMemoryTable[0].VirtualBase =3D VirtualMemoryTable[0].PhysicalB= ase; > + VirtualMemoryTable[0].Length =3D PcdGet64 (PcdSystemMemorySize); > + VirtualMemoryTable[0].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_WRI= TE_BACK; > + > + DEBUG ((DEBUG_INFO, "%a: Dumping System DRAM Memory Map:\n" > + "\tPhysicalBase: 0x%lX\n" > + "\tVirtualBase: 0x%lX\n" > + "\tLength: 0x%lX\n", > + __FUNCTION__, > + VirtualMemoryTable[0].PhysicalBase, > + VirtualMemoryTable[0].VirtualBase, > + VirtualMemoryTable[0].Length)); > + > + // Memory mapped peripherals (UART, RTC, GIC, virtio-mmio, etc) > + VirtualMemoryTable[1].PhysicalBase =3D MACH_VIRT_PERIPH_BASE; > + VirtualMemoryTable[1].VirtualBase =3D MACH_VIRT_PERIPH_BASE; > + VirtualMemoryTable[1].Length =3D MACH_VIRT_PERIPH_SIZE; > + VirtualMemoryTable[1].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_DEV= ICE; > + > + // Map the FV region as normal executable memory > + VirtualMemoryTable[2].PhysicalBase =3D PcdGet64 (PcdFvBaseAddress); > + VirtualMemoryTable[2].VirtualBase =3D VirtualMemoryTable[2].PhysicalB= ase; > + VirtualMemoryTable[2].Length =3D FixedPcdGet32 (PcdFvSize); > + VirtualMemoryTable[2].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_WRI= TE_BACK; > + > + // End of Table > + ZeroMem (&VirtualMemoryTable[3], sizeof (ARM_MEMORY_REGION_DESCRIPTOR)= ); > + > + *VirtualMemoryMap =3D VirtualMemoryTable; > +} > diff --git a/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLibCon= structor.c b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLibConst= ructor.c > new file mode 100644 > index 000000000000..5f89b70df990 > --- /dev/null > +++ b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLibConstructo= r.c > @@ -0,0 +1,100 @@ > +/** @file > + > + Copyright (c) 2014-2017, Linaro Limited. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > + > +RETURN_STATUS > +EFIAPI > +ClhVirtMemInfoPeiLibConstructor ( > + VOID > + ) > +{ > + VOID *DeviceTreeBase; > + INT32 Node, Prev; > + UINT64 NewBase, CurBase; > + UINT64 NewSize, CurSize; > + CONST CHAR8 *Type; > + INT32 Len; > + CONST UINT64 *RegProp; > + RETURN_STATUS PcdStatus; > + > + NewBase =3D 0; > + NewSize =3D 0; > + > + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAd= dress); > + ASSERT (DeviceTreeBase !=3D NULL); > + > + // > + // Make sure we have a valid device tree blob > + // > + ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); > + > + // > + // Look for the lowest memory node > + // > + for (Prev =3D 0;; Prev =3D Node) { > + Node =3D fdt_next_node (DeviceTreeBase, Prev, NULL); > + if (Node < 0) { > + break; > + } > + > + // > + // Check for memory node > + // > + Type =3D fdt_getprop (DeviceTreeBase, Node, "device_type", &Len); > + if (Type && AsciiStrnCmp (Type, "memory", Len) =3D=3D 0) { > + // > + // Get the 'reg' property of this node. For now, we will assume > + // two 8 byte quantities for base and size, respectively. > + // > + RegProp =3D fdt_getprop (DeviceTreeBase, Node, "reg", &Len); > + if (RegProp !=3D 0 && Len =3D=3D (2 * sizeof (UINT64))) { > + > + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); > + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); > + > + DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n", > + __FUNCTION__, CurBase, CurBase + CurSize - 1)); > + > + if (NewBase > CurBase || NewBase =3D=3D 0) { > + NewBase =3D CurBase; > + NewSize =3D CurSize; > + } > + } else { > + DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n", > + __FUNCTION__)); > + } > + } > + } > + > + // > + // Make sure the start of DRAM matches our expectation > + // > + ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) =3D=3D NewBase); > + PcdStatus =3D PcdSet64S (PcdSystemMemorySize, NewSize); > + ASSERT_RETURN_ERROR (PcdStatus); > + > + // > + // We need to make sure that the machine we are running on has at leas= t > + // 128 MB of memory configured, and is currently executing this binary= from > + // NOR flash. This prevents a device tree image in DRAM from getting > + // clobbered when our caller installs permanent PEI RAM, before we hav= e a > + // chance of marking its location as reserved or copy it to a freshly > + // allocated block in the permanent PEI RAM in the platform PEIM. > + // > + ASSERT (NewSize >=3D SIZE_128MB); > + ASSERT ( > + (((UINT64)PcdGet64 (PcdFdBaseAddress) + > + (UINT64)PcdGet32 (PcdFdSize)) <=3D NewBase) || > + ((UINT64)PcdGet64 (PcdFdBaseAddress) >=3D (NewBase + NewSize))); > + > + return RETURN_SUCCESS; > +} > --_000_AM6PR08MB3784BDEF3E7DB1E6885510F484469AM6PR08MB3784eurp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Jianyo= ng,

&nbs= p;

You need to check if you're subscribed to the <= i>EDK II development mailing list. Otherwise, your patch email will get= rejected. You can subscribe here: https://edk2.groups.io/g/devel.

Make sure that you reply to the email with subscript= ion confirmation sent from noreply@groups.io. Unless you do it, you won't become a mem= ber of the mailing list.

I would also recommend that you wait for a day after= confirming, as I believe the edk2.groups.io admin will need to approve you= r membership.

 

Regards,

 

Sami Mujawar

&nbs= p;

From: Laszlo Ersek <le= rsek@redhat.com>
Date: Thursday, 22 April 2021 at 14:57
To: Jianyong Wu <Jianyong.Wu@arm.com>, edk2-devel-groups-io &l= t;devel@edk2.groups.io>
Cc: Justin He <Justin.He@arm.com>, Ard Biesheuvel <ardb+tia= nocore@kernel.org>, Leif Lindholm <leif@nuviainc.com>, Sami Mujawa= r <Sami.Mujawar@arm.com>
Subject: Re: [PATCH v1 1/4] ArmVirtPkg: Library: Memory initializati= on for Cloud Hypervisor

Hi Jianyong,

On 04/22/21 10:24, Jianyong Wu wrote:
> Cloud Hypervisor is kvm based VMM implemented in rust.
>
> This library populates the system memory map for the
> Cloud Hypervisor virtual platform.
>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Leif Lindholm <leif@nuviainc.com>
> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
> ---
>  ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib.inf&nb= sp;         |  47 +++++++++ >  ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoLib.c &n= bsp;            = ; |  94 ++++++++++++++++++
>  ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLibConstru= ctor.c | 100 ++++++++++++++++++++
>  3 files changed, 241 insertions(+)

let's sort out the meta-problems first:

(1) you need a Feature Request BZ for this;
<https://bugzilla.tianocore.= org/>. The commit messages should reference
the specific bugzilla ticket URL.

(2) "Clh" is a catastrophically bad abbreviation. The whole point= of
your work is to add Cloud Hypervisor support, so why trash the most
relevant information in the file names with an inane abbreviation?

(Not to mention that the name "Cloud Hypervisor" itself is as
nondescript as possible. :/)

(3) I have not received a cover letter (0/4). Not sure if you sent one.

(4) I don't see the messages in my edk2-devel folder, or in the mailing
list archives, or in the messages held for moderation at the groups.io
WebUI.

(5) "Cloud Hypervisor" is not something that I can justifiably sp= end
much time on. I'm willing to review this series at the level at which
I've reviewed (for example) XenPVH or Bhyve in the past, mainly focusing on style and potential regressions. However, that's not enough for the
long term: someone from ARM (or elsewhere) will have to step up for
permanent reviewership. Please add a patch for extending
"Maintainers.txt" appropriately. Example subsystems:

- ArmVirtPkg: modules used on Xen
- ArmVirtPkg: Kvmtool emulated platform support
- OvmfPkg: bhyve-related modules
- OvmfPkg: Xen-related modules

Please keep the subsystem titles alphabetically sorted in the file.

Please resend.

(I'm posting these comments at once because they are understandable to
the community even in the absence of your patches on the list.)

Thanks
Laszlo

>
> diff --git a/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib= .inf b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib.inf
> new file mode 100644
> index 000000000000..04cb1f2a581a
> --- /dev/null
> +++ b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib.inf > @@ -0,0 +1,47 @@
> +#/* @file
> +#
> +#  Copyright (c) 2011-2015, ARM Limited. All rights reserved. > +#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.=
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#*/
> +
> +[Defines]
> +  INF_VERSION        &nb= sp;           =3D 0x00010= 01A
> +  BASE_NAME         = ;             = =3D ClhVirtMemInfoPeiLib
> +  FILE_GUID         = ;             = =3D 3E29D940-0591-EE6A-CAD4-223A9CF55E75
> +  MODULE_TYPE        &nb= sp;           =3D BASE > +  VERSION_STRING        =          =3D 1.0
> +  LIBRARY_CLASS        &= nbsp;         =3D ArmVirtMemInfoLib= |PEIM
> +  CONSTRUCTOR        &nb= sp;           =3D ClhVirt= MemInfoPeiLibConstructor
> +
> +[Sources]
> +  ClhVirtMemInfoLib.c
> +  ClhVirtMemInfoPeiLibConstructor.c
> +
> +[Packages]
> +  ArmPkg/ArmPkg.dec
> +  ArmVirtPkg/ArmVirtPkg.dec
> +  EmbeddedPkg/EmbeddedPkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> +  ArmLib
> +  BaseMemoryLib
> +  DebugLib
> +  FdtLib
> +  PcdLib
> +  MemoryAllocationLib
> +
> +[Pcd]
> +  gArmTokenSpaceGuid.PcdFdBaseAddress
> +  gArmTokenSpaceGuid.PcdFvBaseAddress
> +  gArmTokenSpaceGuid.PcdSystemMemoryBase
> +  gArmTokenSpaceGuid.PcdSystemMemorySize
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdFdSize
> +  gArmTokenSpaceGuid.PcdFvSize
> +  gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
> diff --git a/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoLib.c = b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoLib.c
> new file mode 100644
> index 000000000000..829d7d7aa259
> --- /dev/null
> +++ b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoLib.c
> @@ -0,0 +1,94 @@
> +/** @file
> +
> +  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.<= br> > +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/ArmLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +
> +// Number of Virtual Memory Map Descriptors
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS    &nb= sp;     5
> +
> +//
> +// mach-virt's core peripherals such as the UART, the GIC and the RTC= are
> +// all mapped in the 'miscellaneous device I/O' region, which we just= map
> +// in its entirety rather than device by device. Note that it does no= t
> +// cover any of the NOR flash banks or PCI resource windows.
> +//
> +#define MACH_VIRT_PERIPH_BASE       0x0= 8000000
> +#define MACH_VIRT_PERIPH_SIZE       SIZ= E_128MB
> +
> +//
> +// in cloud-hypervisor, 0x0 ~ 0x8000000 is reserved as normal memory = for UEFI
> +//
> +#define CLH_UEFI_MEM_BASE       0x0
> +#define CLH_UEFI_MEM_SIZE       0x08000= 000
> +
> +/**
> +  Return the Virtual Memory Map of your platform
> +
> +  This Virtual Memory Map is used by MemoryInitPei Module to ini= tialize the MMU
> +  on your platform.
> +
> +  @param[out]   VirtualMemoryMap    Arr= ay of ARM_MEMORY_REGION_DESCRIPTOR
> +           &nb= sp;            =             describi= ng a Physical-to-Virtual Memory
> +           &nb= sp;            =             mapping.= This array must be ended by a
> +           &nb= sp;            =             zero-fil= led entry. The allocated memory
> +           &nb= sp;            =             will not= be freed.
> +
> +**/
> +VOID
> +ArmVirtGetMemoryMap (
> +  OUT ARM_MEMORY_REGION_DESCRIPTOR   **VirtualMemoryMa= p
> +  )
> +{
> +  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
> +
> +  ASSERT (VirtualMemoryMap !=3D NULL);
> +
> +  VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION= _DESCRIPTOR) *
> +           &nb= sp;            =              MA= X_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> +  if (VirtualMemoryTable =3D=3D NULL) {
> +    DEBUG ((DEBUG_ERROR, "%a: Error: Failed Alloc= atePool()\n", __FUNCTION__));
> +    return;
> +  }
> +
> +  // System DRAM
> +  VirtualMemoryTable[0].PhysicalBase =3D PcdGet64 (PcdSystemMemo= ryBase);
> +  VirtualMemoryTable[0].VirtualBase  =3D VirtualMemoryTable= [0].PhysicalBase;
> +  VirtualMemoryTable[0].Length     &nbs= p; =3D PcdGet64 (PcdSystemMemorySize);
> +  VirtualMemoryTable[0].Attributes   =3D ARM_MEMORY_RE= GION_ATTRIBUTE_WRITE_BACK;
> +
> +  DEBUG ((DEBUG_INFO, "%a: Dumping System DRAM Memory Map:\= n"
> +      "\tPhysicalBase: 0x%lX\n" > +      "\tVirtualBase: 0x%lX\n"
> +      "\tLength: 0x%lX\n",
> +      __FUNCTION__,
> +      VirtualMemoryTable[0].PhysicalBase, > +      VirtualMemoryTable[0].VirtualBase,
> +      VirtualMemoryTable[0].Length));
> +
> +  // Memory mapped peripherals (UART, RTC, GIC, virtio-mmio, etc= )
> +  VirtualMemoryTable[1].PhysicalBase =3D MACH_VIRT_PERIPH_BASE;<= br> > +  VirtualMemoryTable[1].VirtualBase  =3D MACH_VIRT_PERIPH_B= ASE;
> +  VirtualMemoryTable[1].Length     &nbs= p; =3D MACH_VIRT_PERIPH_SIZE;
> +  VirtualMemoryTable[1].Attributes   =3D ARM_MEMORY_RE= GION_ATTRIBUTE_DEVICE;
> +
> +  // Map the FV region as normal executable memory
> +  VirtualMemoryTable[2].PhysicalBase =3D PcdGet64 (PcdFvBaseAddr= ess);
> +  VirtualMemoryTable[2].VirtualBase  =3D VirtualMemoryTable= [2].PhysicalBase;
> +  VirtualMemoryTable[2].Length     &nbs= p; =3D FixedPcdGet32 (PcdFvSize);
> +  VirtualMemoryTable[2].Attributes   =3D ARM_MEMORY_RE= GION_ATTRIBUTE_WRITE_BACK;
> +
> +  // End of Table
> +  ZeroMem (&VirtualMemoryTable[3], sizeof (ARM_MEMORY_REGION= _DESCRIPTOR));
> +
> +  *VirtualMemoryMap =3D VirtualMemoryTable;
> +}
> diff --git a/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLib= Constructor.c b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLibCo= nstructor.c
> new file mode 100644
> index 000000000000..5f89b70df990
> --- /dev/null
> +++ b/ArmVirtPkg/Library/ClhVirtMemInfoLib/ClhVirtMemInfoPeiLibConstru= ctor.c
> @@ -0,0 +1,100 @@
> +/** @file
> +
> +  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.<= br> > +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <libfdt.h>
> +
> +RETURN_STATUS
> +EFIAPI
> +ClhVirtMemInfoPeiLibConstructor (
> +  VOID
> +  )
> +{
> +  VOID          *De= viceTreeBase;
> +  INT32         Node, Pr= ev;
> +  UINT64        NewBase, CurB= ase;
> +  UINT64        NewSize, CurS= ize;
> +  CONST CHAR8   *Type;
> +  INT32         Len;
> +  CONST UINT64  *RegProp;
> +  RETURN_STATUS PcdStatus;
> +
> +  NewBase =3D 0;
> +  NewSize =3D 0;
> +
> +  DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeIniti= alBaseAddress);
> +  ASSERT (DeviceTreeBase !=3D NULL);
> +
> +  //
> +  // Make sure we have a valid device tree blob
> +  //
> +  ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0);
> +
> +  //
> +  // Look for the lowest memory node
> +  //
> +  for (Prev =3D 0;; Prev =3D Node) {
> +    Node =3D fdt_next_node (DeviceTreeBase, Prev, NULL= );
> +    if (Node < 0) {
> +      break;
> +    }
> +
> +    //
> +    // Check for memory node
> +    //
> +    Type =3D fdt_getprop (DeviceTreeBase, Node, "= device_type", &Len);
> +    if (Type && AsciiStrnCmp (Type, "memo= ry", Len) =3D=3D 0) {
> +      //
> +      // Get the 'reg' property of this node= . For now, we will assume
> +      // two 8 byte quantities for base and = size, respectively.
> +      //
> +      RegProp =3D fdt_getprop (DeviceTreeBas= e, Node, "reg", &Len);
> +      if (RegProp !=3D 0 && Len =3D= =3D (2 * sizeof (UINT64))) {
> +
> +        CurBase =3D fdt64_to_cpu (= ReadUnaligned64 (RegProp));
> +        CurSize =3D fdt64_to_cpu (= ReadUnaligned64 (RegProp + 1));
> +
> +        DEBUG ((DEBUG_INFO, "= %a: System RAM @ 0x%lx - 0x%lx\n",
> +          __FUNCTION__, = CurBase, CurBase + CurSize - 1));
> +
> +        if (NewBase > CurBase |= | NewBase =3D=3D 0) {
> +          NewBase =3D Cu= rBase;
> +          NewSize =3D Cu= rSize;
> +        }
> +      } else {
> +        DEBUG ((DEBUG_ERROR, "= ;%a: Failed to parse FDT memory node\n",
> +          __FUNCTION__))= ;
> +      }
> +    }
> +  }
> +
> +  //
> +  // Make sure the start of DRAM matches our expectation
> +  //
> +  ASSERT (FixedPcdGet64 (PcdSystemMemoryBase) =3D=3D NewBase); > +  PcdStatus =3D PcdSet64S (PcdSystemMemorySize, NewSize);
> +  ASSERT_RETURN_ERROR (PcdStatus);
> +
> +  //
> +  // We need to make sure that the machine we are running on has= at least
> +  // 128 MB of memory configured, and is currently executing thi= s binary from
> +  // NOR flash. This prevents a device tree image in DRAM from g= etting
> +  // clobbered when our caller installs permanent PEI RAM, befor= e we have a
> +  // chance of marking its location as reserved or copy it to a = freshly
> +  // allocated block in the permanent PEI RAM in the platform PE= IM.
> +  //
> +  ASSERT (NewSize >=3D SIZE_128MB);
> +  ASSERT (
> +    (((UINT64)PcdGet64 (PcdFdBaseAddress) +
> +      (UINT64)PcdGet32 (PcdFdSize)) <=3D = NewBase) ||
> +    ((UINT64)PcdGet64 (PcdFdBaseAddress) >=3D (NewB= ase + NewSize)));
> +
> +  return RETURN_SUCCESS;
> +}
>

--_000_AM6PR08MB3784BDEF3E7DB1E6885510F484469AM6PR08MB3784eurp_--