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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Aug 2022 13:46:48.8668 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d363a1a-0a12-49d6-5b03-08da7b9ff064 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT055.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3920 Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_AS4PR08MB80477A3F065666B4AEFD781E86649AS4PR08MB8047eurp_" --_000_AS4PR08MB80477A3F065666B4AEFD781E86649AS4PR08MB8047eurp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hey Sami, This code is shared between all the variants of the Sgi platform. Depending upon the variant, there will be a different number of CPUs presen= t on it. To handle this I have written the code in a generic way. The Dsdt containing AML code describing Cluster topology does not have any = field for CPU state. AFAIK, the MADT table is used to check if the CPU is enabled and to get its= MPID number. I have tested this code and cat /proc/cpuinfo does not show disabled CPUs i= n the list. linux/processor_core.c at master =B7 torvalds/linux (github.com) thi= s is the code that maps the logical id to the MPID number. Regards, Nishant ________________________________ From: Sami Mujawar Sent: Monday, August 8, 2022 10:11 AM To: Nishant Sharma ; devel@edk2.groups.io Subject: Re: [edk2-devel] [edk2-platforms] [PATCH 1/1] Platform/Sgi: Add su= pport to disable isolated cpus Hi Nishant, The parsing code would be much clear if you define a GIC substructure heade= r (if not already present) and then traverse the data. To add to this your patch does not address the AML code which still says th= at the CPU is enabled. You would need to update the AML code in this patch = otherwise you end up having inconsistent view of the CPU state. Regards, Sami Mujawar From: Nishant Sharma Date: Friday, 5 August 2022 at 12:19 To: Sami Mujawar , "devel@edk2.groups.io" Subject: Re: [edk2-devel] [edk2-platforms] [PATCH 1/1] Platform/Sgi: Add su= pport to disable isolated cpus Hi Sami, Please find my response inline On Thu, Jul 28, 2022 at 06:12 PM, Sami Mujawar wrote: Hi Nishant, Please find my response inline marked [SAMI]. Regards, Sami Mujawar On 27/07/2022 02:53 pm, Nishant Sharma wrote: Hi Sami, Please find my reply inline On Thu, Jul 21, 2022 at 12:47 PM, Sami Mujawar wrote: Hi Nishant, Please find my response inline marked [SAMI]. Regards, Sami Mujawar On 17/06/2022 07:07 am, Nishant Sharma wrote: Isolated CPUs are those that are not to be used on the platform for various reasons. The isolated CPU list is an array of MPID values of [SAMI] Can you explain the use-case/reason, please? [Nishant]: I will update in the next patchset. the CPUs that have to be isolated. This list is supplied via the NT_FW_CONFIG dtb. Add support to search for isolated CPUs MPID list and, if present, update the MADT table to disable the corresponding CPUs. Signed-off-by: Nishant Sharma --- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 1 - Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf | 8 +- Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++ Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 131 ++++++= +++++++++++++- Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c | 45 ++++++= - 5 files changed, 186 insertions(+), 6 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf index 4b36c3e5ceb2..e13c2f08ce6e 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf @@ -18,7 +18,6 @@ Dbg2.aslc Fadt.aslc Gtdt.aslc - Iort.aslc [SAMI] Why is IORT table being removed here? [Nishant]: I think some issue with patch generation. I will remove this cha= nge in the next patch. Thanks for pointing it out. Mcfg.aslc RdN2Cfg1/Dsdt.asl RdN2Cfg1/Madt.aslc diff --git a/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf = b/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf index 407160c07563..fbf061ad3bdb 100644 --- a/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf +++ b/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited. All rights reserved. +# Copyright (c) 2018-2022, ARM Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -13,6 +13,7 @@ ENTRY_POINT =3D SgiPlatformPeim [Packages] + ArmPlatformPkg/ArmPlatformPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec Platform/ARM/SgiPkg/SgiPlatform.dec @@ -21,6 +22,11 @@ FdtLib PeimEntryPoint +[FixedPcd] + gArmSgiTokenSpaceGuid.PcdChipCount + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + [Sources] SgiPlatformPeim.c diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPk= g/Include/SgiPlatform.h index dddb58832d73..311286ce5337 100644 --- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h +++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h @@ -65,11 +65,18 @@ #define DRAM_BLOCK2_BASE_REMOTE(ChipId) \ (SGI_REMOTE_CHIP_MEM_OFFSET (ChipId) + FixedPcdGet64 (PcdDramBlo= ck2Base)) +// List of isolated CPUs MPID +typedef struct { + UINT64 Count; // Number of elements present in the list + UINT64 Mpid[]; // List containing isolated CPU MPIDs +} SGI_ISOLATED_CPU_LIST; + // ARM platform description data. typedef struct { UINTN PlatformId; UINTN ConfigId; UINTN MultiChipMode; + SGI_ISOLATED_CPU_LIST IsolatedCpuList; } SGI_PLATFORM_DESCRIPTOR; // Arm SGI/RD Product IDs diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platfo= rm/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c index 2f72e7152ff3..80190120ff32 100644 --- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c +++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c @@ -1,14 +1,17 @@ /** @file * -* Copyright (c) 2018, ARM Limited. All rights reserved. +* Copyright (c) 2018 - 2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * **/ +#include + #include #include #include +#include #include VOID @@ -16,6 +19,127 @@ InitVirtioDevices ( VOID ); +/** + Search for a MPID in a list + + Performs a linear search for a specified MPID on the given linear + list of MPIDs. + + @param[in] MpidList Pointer to list. + @param[in] Count Number of the elements in the list. + @param[in] Mpid Target MPID. + + @retval TRUE MPID is present. + @retval FALSE MPID is not present. +**/ +STATIC +BOOLEAN +CheckIfMpidIsPresent ( + IN UINT64 *MpidList, + IN UINT64 Count, + IN UINT64 Mpid + ) +{ + UINT64 Idx; + + for (Idx =3D 0; Idx < Count; Idx++) { + if (MpidList[Idx] =3D=3D Mpid) { + return TRUE; + } + } + + return FALSE; +} + +/** + Disables isolated CPUs in the MADT table + + Parse the IsolatedCpuInfo from the Hob list and updates the MADT table t= o [SAMI] Nit. updates -> update [Nishant] Will update in next patch version. + disable cpu's which are not available on the platfrom. + + @param[in] AcpiHeader Points to the Madt table. + @param[in] HobData Points to the unusable cpuinfo in hoblist. +**/ +STATIC +VOID +UpdateMadtTable ( + IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader, + IN SGI_PLATFORM_DESCRIPTOR *HobData + ) +{ + UINT8 *StructureListHead; + UINT8 *StructureListTail; + EFI_ACPI_6_4_GIC_STRUCTURE *GicStructure; + BOOLEAN MpidPresent; + + if (HobData->IsolatedCpuList.Count =3D=3D 0) { + return; + } + + StructureListHead =3D + ((UINT8 *)AcpiHeader) + + sizeof(EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); + StructureListTail =3D (UINT8 *)AcpiHeader + AcpiHeader->Length; + + // Locate ACPI GICC structure in the MADT table. + while (StructureListHead < StructureListTail) { + if (StructureListHead[0] =3D=3D EFI_ACPI_6_4_GIC) { [SAMI] This is definitely not the way to parse an ACPI table. Please dont d= o this. Also, why are you not using DynamicTables framework? It is designed to hand= le such cases. [/SAMI] [Nishant] Could you please add more details on what is wrong with this approach? [SAMI] The problem is it does not work with the ACPI table below: [snip] /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20210930 (32-bit version) * Copyright (c) 2000 - 2021 Intel Corporation * * Disassembly of apic0000.bin, Thu Jul 28 17:57:00 2022 * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in= hex) */ [000h 0000 4] Signature : "APIC" [Multiple APIC Des= cription Table (MADT)] [004h 0004 4] Table Length : 000005FC [008h 0008 1] Revision : 05 [009h 0009 1] Checksum : 0B [00Ah 0010 6] Oem ID : "ARMLTD" [010h 0016 8] Oem Table ID : "ARMSGI " [018h 0024 4] Oem Revision : 20220728 [01Ch 0028 4] Asl Compiler ID : "ARM " [020h 0032 4] Asl Compiler Revision : 00002999 [024h 0036 4] Local Apic Address : 00000000 [028h 0040 4] Flags (decoded below) : 00000000 PC-AT Compatibility : 0 [02Ch 0044 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [02Dh 0045 1] Length : 50 [02Eh 0046 2] Reserved : 0000 [030h 0048 4] CPU Interface Number : 00000000 [034h 0052 4] Processor UID : 00000000 [038h 0056 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [03Ch 0060 4] Parking Protocol Version : 00000000 [040h 0064 4] Performance Interrupt : 00000017 [044h 0068 8] Parked Address : 0000000000000000 [04Ch 0076 8] Base Address : 0000000000000000 [054h 0084 8] Virtual GIC Base Address : 0000000000000000 [05Ch 0092 8] Hypervisor GIC Base Address : 0000000000000000 [064h 0100 4] Virtual GIC Interrupt : 00000019 [068h 0104 8] Redistributor Base Address : 0000000000000000 [070h 0112 8] ARM MPIDR : 0000000000000000 [078h 0120 1] Efficiency Class : 00 [079h 0121 1] Reserved : 00 [07Ah 0122 2] SPE Overflow Interrupt : 0000 [07Ch 0124 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [07Dh 0125 1] Length : 50 [07Eh 0126 2] Reserved : 0000 [080h 0128 4] CPU Interface Number : 00000000 [084h 0132 4] Processor UID : 00000001 [088h 0136 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [08Ch 0140 4] Parking Protocol Version : 00000000 [090h 0144 4] Performance Interrupt : 00000017 [094h 0148 8] Parked Address : 0000000000000000 [09Ch 0156 8] Base Address : 0000000000000000 [0A4h 0164 8] Virtual GIC Base Address : 0000000000000000 [0ACh 0172 8] Hypervisor GIC Base Address : 0000000000000000 [0B4h 0180 4] Virtual GIC Interrupt : 00000019 [0B8h 0184 8] Redistributor Base Address : 0000000000000000 [0C0h 0192 8] ARM MPIDR : 0000000000010000 [0C8h 0200 1] Efficiency Class : 00 [0C9h 0201 1] Reserved : 00 [0CAh 0202 2] SPE Overflow Interrupt : 0000 [0CCh 0204 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [0CDh 0205 1] Length : 50 [0CEh 0206 2] Reserved : 0000 [0D0h 0208 4] CPU Interface Number : 00000000 [0D4h 0212 4] Processor UID : 00000002 [0D8h 0216 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [0DCh 0220 4] Parking Protocol Version : 00000000 [0E0h 0224 4] Performance Interrupt : 00000017 [0E4h 0228 8] Parked Address : 0000000000000000 [0ECh 0236 8] Base Address : 0000000000000000 [0F4h 0244 8] Virtual GIC Base Address : 0000000000000000 [0FCh 0252 8] Hypervisor GIC Base Address : 0000000000000000 [104h 0260 4] Virtual GIC Interrupt : 00000019 [108h 0264 8] Redistributor Base Address : 0000000000000000 [110h 0272 8] ARM MPIDR : 0000000000020000 [118h 0280 1] Efficiency Class : 00 [119h 0281 1] Reserved : 00 [11Ah 0282 2] SPE Overflow Interrupt : 0000 [11Ch 0284 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [11Dh 0285 1] Length : 50 [11Eh 0286 2] Reserved : 0000 [120h 0288 4] CPU Interface Number : 00000000 [124h 0292 4] Processor UID : 00000003 [128h 0296 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [12Ch 0300 4] Parking Protocol Version : 00000000 [130h 0304 4] Performance Interrupt : 00000017 [134h 0308 8] Parked Address : 0000000000000000 [13Ch 0316 8] Base Address : 0000000000000000 [144h 0324 8] Virtual GIC Base Address : 0000000000000000 [14Ch 0332 8] Hypervisor GIC Base Address : 0000000000000000 [154h 0340 4] Virtual GIC Interrupt : 00000019 [158h 0344 8] Redistributor Base Address : 0000000000000000 [160h 0352 8] ARM MPIDR : 0000000000030000 [168h 0360 1] Efficiency Class : 00 [169h 0361 1] Reserved : 00 [16Ah 0362 2] SPE Overflow Interrupt : 0000 [16Ch 0364 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [16Dh 0365 1] Length : 50 [16Eh 0366 2] Reserved : 0000 [170h 0368 4] CPU Interface Number : 00000000 [174h 0372 4] Processor UID : 00000004 [178h 0376 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [17Ch 0380 4] Parking Protocol Version : 00000000 [180h 0384 4] Performance Interrupt : 00000017 [184h 0388 8] Parked Address : 0000000000000000 [18Ch 0396 8] Base Address : 0000000000000000 [194h 0404 8] Virtual GIC Base Address : 0000000000000000 [19Ch 0412 8] Hypervisor GIC Base Address : 0000000000000000 [1A4h 0420 4] Virtual GIC Interrupt : 00000019 [1A8h 0424 8] Redistributor Base Address : 0000000000000000 [1B0h 0432 8] ARM MPIDR : 0000000100000000 [1B8h 0440 1] Efficiency Class : 00 [1B9h 0441 1] Reserved : 00 [1BAh 0442 2] SPE Overflow Interrupt : 0000 [1BCh 0444 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [1BDh 0445 1] Length : 50 [1BEh 0446 2] Reserved : 0000 [1C0h 0448 4] CPU Interface Number : 00000000 [1C4h 0452 4] Processor UID : 00000005 [1C8h 0456 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [1CCh 0460 4] Parking Protocol Version : 00000000 [1D0h 0464 4] Performance Interrupt : 00000017 [1D4h 0468 8] Parked Address : 0000000000000000 [1DCh 0476 8] Base Address : 0000000000000000 [1E4h 0484 8] Virtual GIC Base Address : 0000000000000000 [1ECh 0492 8] Hypervisor GIC Base Address : 0000000000000000 [1F4h 0500 4] Virtual GIC Interrupt : 00000019 [1F8h 0504 8] Redistributor Base Address : 0000000000000000 [200h 0512 8] ARM MPIDR : 0000000100010000 [208h 0520 1] Efficiency Class : 00 [209h 0521 1] Reserved : 00 [20Ah 0522 2] SPE Overflow Interrupt : 0000 [20Ch 0524 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [20Dh 0525 1] Length : 50 [20Eh 0526 2] Reserved : 0000 [210h 0528 4] CPU Interface Number : 00000000 [214h 0532 4] Processor UID : 00000006 [218h 0536 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [21Ch 0540 4] Parking Protocol Version : 00000000 [220h 0544 4] Performance Interrupt : 00000017 [224h 0548 8] Parked Address : 0000000000000000 [22Ch 0556 8] Base Address : 0000000000000000 [234h 0564 8] Virtual GIC Base Address : 0000000000000000 [23Ch 0572 8] Hypervisor GIC Base Address : 0000000000000000 [244h 0580 4] Virtual GIC Interrupt : 00000019 [248h 0584 8] Redistributor Base Address : 0000000000000000 [250h 0592 8] ARM MPIDR : 0000000100020000 [258h 0600 1] Efficiency Class : 00 [259h 0601 1] Reserved : 00 [25Ah 0602 2] SPE Overflow Interrupt : 0000 [25Ch 0604 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [25Dh 0605 1] Length : 50 [25Eh 0606 2] Reserved : 0000 [260h 0608 4] CPU Interface Number : 00000000 [264h 0612 4] Processor UID : 00000007 [268h 0616 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [26Ch 0620 4] Parking Protocol Version : 00000000 [270h 0624 4] Performance Interrupt : 00000017 [274h 0628 8] Parked Address : 0000000000000000 [27Ch 0636 8] Base Address : 0000000000000000 [284h 0644 8] Virtual GIC Base Address : 0000000000000000 [28Ch 0652 8] Hypervisor GIC Base Address : 0000000000000000 [294h 0660 4] Virtual GIC Interrupt : 00000019 [298h 0664 8] Redistributor Base Address : 0000000000000000 [2A0h 0672 8] ARM MPIDR : 0000000100030000 [2A8h 0680 1] Efficiency Class : 00 [2A9h 0681 1] Reserved : 00 [2AAh 0682 2] SPE Overflow Interrupt : 0000 [2ACh 0684 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [2ADh 0685 1] Length : 50 [2AEh 0686 2] Reserved : 0000 [2B0h 0688 4] CPU Interface Number : 00000000 [2B4h 0692 4] Processor UID : 00000008 [2B8h 0696 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [2BCh 0700 4] Parking Protocol Version : 00000000 [2C0h 0704 4] Performance Interrupt : 00000017 [2C4h 0708 8] Parked Address : 0000000000000000 [2CCh 0716 8] Base Address : 0000000000000000 [2D4h 0724 8] Virtual GIC Base Address : 0000000000000000 [2DCh 0732 8] Hypervisor GIC Base Address : 0000000000000000 [2E4h 0740 4] Virtual GIC Interrupt : 00000019 [2E8h 0744 8] Redistributor Base Address : 0000000000000000 [2F0h 0752 8] ARM MPIDR : 0000000200000000 [2F8h 0760 1] Efficiency Class : 00 [2F9h 0761 1] Reserved : 00 [2FAh 0762 2] SPE Overflow Interrupt : 0000 [2FCh 0764 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [2FDh 0765 1] Length : 50 [2FEh 0766 2] Reserved : 0000 [300h 0768 4] CPU Interface Number : 00000000 [304h 0772 4] Processor UID : 00000009 [308h 0776 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [30Ch 0780 4] Parking Protocol Version : 00000000 [310h 0784 4] Performance Interrupt : 00000017 [314h 0788 8] Parked Address : 0000000000000000 [31Ch 0796 8] Base Address : 0000000000000000 [324h 0804 8] Virtual GIC Base Address : 0000000000000000 [32Ch 0812 8] Hypervisor GIC Base Address : 0000000000000000 [334h 0820 4] Virtual GIC Interrupt : 00000019 [338h 0824 8] Redistributor Base Address : 0000000000000000 [340h 0832 8] ARM MPIDR : 0000000200010000 [348h 0840 1] Efficiency Class : 00 [349h 0841 1] Reserved : 00 [34Ah 0842 2] SPE Overflow Interrupt : 0000 [34Ch 0844 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [34Dh 0845 1] Length : 50 [34Eh 0846 2] Reserved : 0000 [350h 0848 4] CPU Interface Number : 00000000 [354h 0852 4] Processor UID : 0000000A [358h 0856 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [35Ch 0860 4] Parking Protocol Version : 00000000 [360h 0864 4] Performance Interrupt : 00000017 [364h 0868 8] Parked Address : 0000000000000000 [36Ch 0876 8] Base Address : 0000000000000000 [374h 0884 8] Virtual GIC Base Address : 0000000000000000 [37Ch 0892 8] Hypervisor GIC Base Address : 0000000000000000 [384h 0900 4] Virtual GIC Interrupt : 00000019 [388h 0904 8] Redistributor Base Address : 0000000000000000 [390h 0912 8] ARM MPIDR : 0000000200020000 [398h 0920 1] Efficiency Class : 00 [399h 0921 1] Reserved : 00 [39Ah 0922 2] SPE Overflow Interrupt : 0000 [39Ch 0924 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [39Dh 0925 1] Length : 50 [39Eh 0926 2] Reserved : 0000 [3A0h 0928 4] CPU Interface Number : 00000000 [3A4h 0932 4] Processor UID : 0000000B [3A8h 0936 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [3ACh 0940 4] Parking Protocol Version : 00000000 [3B0h 0944 4] Performance Interrupt : 00000017 [3B4h 0948 8] Parked Address : 0000000000000000 [3BCh 0956 8] Base Address : 0000000000000000 [3C4h 0964 8] Virtual GIC Base Address : 0000000000000000 [3CCh 0972 8] Hypervisor GIC Base Address : 0000000000000000 [3D4h 0980 4] Virtual GIC Interrupt : 00000019 [3D8h 0984 8] Redistributor Base Address : 0000000000000000 [3E0h 0992 8] ARM MPIDR : 0000000200030000 [3E8h 1000 1] Efficiency Class : 00 [3E9h 1001 1] Reserved : 00 [3EAh 1002 2] SPE Overflow Interrupt : 0000 [3ECh 1004 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [3EDh 1005 1] Length : 50 [3EEh 1006 2] Reserved : 0000 [3F0h 1008 4] CPU Interface Number : 00000000 [3F4h 1012 4] Processor UID : 0000000C [3F8h 1016 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [3FCh 1020 4] Parking Protocol Version : 00000000 [400h 1024 4] Performance Interrupt : 00000017 [404h 1028 8] Parked Address : 0000000000000000 [40Ch 1036 8] Base Address : 0000000000000000 [414h 1044 8] Virtual GIC Base Address : 0000000000000000 [41Ch 1052 8] Hypervisor GIC Base Address : 0000000000000000 [424h 1060 4] Virtual GIC Interrupt : 00000019 [428h 1064 8] Redistributor Base Address : 0000000000000000 [430h 1072 8] ARM MPIDR : 0000000300000000 [438h 1080 1] Efficiency Class : 00 [439h 1081 1] Reserved : 00 [43Ah 1082 2] SPE Overflow Interrupt : 0000 [43Ch 1084 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [43Dh 1085 1] Length : 50 [43Eh 1086 2] Reserved : 0000 [440h 1088 4] CPU Interface Number : 00000000 [444h 1092 4] Processor UID : 0000000D [448h 1096 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [44Ch 1100 4] Parking Protocol Version : 00000000 [450h 1104 4] Performance Interrupt : 00000017 [454h 1108 8] Parked Address : 0000000000000000 [45Ch 1116 8] Base Address : 0000000000000000 [464h 1124 8] Virtual GIC Base Address : 0000000000000000 [46Ch 1132 8] Hypervisor GIC Base Address : 0000000000000000 [474h 1140 4] Virtual GIC Interrupt : 00000019 [478h 1144 8] Redistributor Base Address : 0000000000000000 [480h 1152 8] ARM MPIDR : 0000000300010000 [488h 1160 1] Efficiency Class : 00 [489h 1161 1] Reserved : 00 [48Ah 1162 2] SPE Overflow Interrupt : 0000 [48Ch 1164 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [48Dh 1165 1] Length : 50 [48Eh 1166 2] Reserved : 0000 [490h 1168 4] CPU Interface Number : 00000000 [494h 1172 4] Processor UID : 0000000E [498h 1176 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [49Ch 1180 4] Parking Protocol Version : 00000000 [4A0h 1184 4] Performance Interrupt : 00000017 [4A4h 1188 8] Parked Address : 0000000000000000 [4ACh 1196 8] Base Address : 0000000000000000 [4B4h 1204 8] Virtual GIC Base Address : 0000000000000000 [4BCh 1212 8] Hypervisor GIC Base Address : 0000000000000000 [4C4h 1220 4] Virtual GIC Interrupt : 00000019 [4C8h 1224 8] Redistributor Base Address : 0000000000000000 [4D0h 1232 8] ARM MPIDR : 0000000300020000 [4D8h 1240 1] Efficiency Class : 00 [4D9h 1241 1] Reserved : 00 [4DAh 1242 2] SPE Overflow Interrupt : 0000 [4DCh 1244 1] Subtable Type : 0B [Generic Interrupt Contro= ller] [4DDh 1245 1] Length : 50 [4DEh 1246 2] Reserved : 0000 [4E0h 1248 4] CPU Interface Number : 00000000 [4E4h 1252 4] Processor UID : 0000000F [4E8h 1256 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Performance Interrupt Trigger Mode : 0 Virtual GIC Interrupt Trigger Mode : 0 [4ECh 1260 4] Parking Protocol Version : 00000000 [4F0h 1264 4] Performance Interrupt : 00000017 [4F4h 1268 8] Parked Address : 0000000000000000 [4FCh 1276 8] Base Address : 0000000000000000 [504h 1284 8] Virtual GIC Base Address : 0000000000000000 [50Ch 1292 8] Hypervisor GIC Base Address : 0000000000000000 [514h 1300 4] Virtual GIC Interrupt : 00000019 [518h 1304 8] Redistributor Base Address : 0000000000000000 [520h 1312 8] ARM MPIDR : 0000000300030000 [528h 1320 1] Efficiency Class : 00 [529h 1321 1] Reserved : 00 [52Ah 1322 2] SPE Overflow Interrupt : 0000 [52Ch 1324 1] Subtable Type : 0C [Generic Interrupt Distri= butor] [52Dh 1325 1] Length : 18 [52Eh 1326 2] Reserved : 0000 [530h 1328 4] Local GIC Hardware ID : 00000000 [534h 1332 8] Base Address : 0000000030000000 [53Ch 1340 4] Interrupt Base : 00000000 [540h 1344 1] Version : 03 [541h 1345 3] Reserved : 000000 [544h 1348 1] Subtable Type : 0E [Generic Interrupt Redist= ributor] [545h 1349 1] Length : 10 [546h 1350 2] Reserved : 0000 [548h 1352 8] Base Address : 00000000301C0000 [550h 1360 4] Length : 01000000 [554h 1364 1] Subtable Type : 0E [Generic Interrupt Redist= ributor] [555h 1365 1] Length : 10 [556h 1366 2] Reserved : 0000 [558h 1368 8] Base Address : 00000400301C0000 [560h 1376 4] Length : 01000000 [564h 1380 1] Subtable Type : 0E [Generic Interrupt Redist= ributor] [565h 1381 1] Length : 10 [566h 1382 2] Reserved : 0000 [568h 1384 8] Base Address : 00000800301C0000 [570h 1392 4] Length : 01000000 [574h 1396 1] Subtable Type : 0E [Generic Interrupt Redist= ributor] [575h 1397 1] Length : 10 [576h 1398 2] Reserved : 0000 [578h 1400 8] Base Address : 00000C00301C0000 [580h 1408 4] Length : 01000000 [584h 1412 1] Subtable Type : 0F [Generic Interrupt Transl= ator] [585h 1413 1] Length : 14 [586h 1414 2] Reserved : 0000 [588h 1416 4] Translation ID : 00000000 [58Ch 1420 8] Base Address : 0000000030040000 [594h 1428 4] Reserved : 00000000 [598h 1432 1] Subtable Type : 0F [Generic Interrupt Transl= ator] [599h 1433 1] Length : 14 [59Ah 1434 2] Reserved : 0000 [59Ch 1436 4] Translation ID : 00000001 [5A0h 1440 8] Base Address : 0000000030080000 [5A8h 1448 4] Reserved : 00000000 [5ACh 1452 1] Subtable Type : 0F [Generic Interrupt Transl= ator] [5ADh 1453 1] Length : 14 [5AEh 1454 2] Reserved : 0000 [5B0h 1456 4] Translation ID : 00000002 [5B4h 1460 8] Base Address : 00000000300C0000 [5BCh 1468 4] Reserved : 00000000 [5C0h 1472 1] Subtable Type : 0F [Generic Interrupt Transl= ator] [5C1h 1473 1] Length : 14 [5C2h 1474 2] Reserved : 0000 [5C4h 1476 4] Translation ID : 00000003 [5C8h 1480 8] Base Address : 0000000030100000 [5D0h 1488 4] Reserved : 00000000 [5D4h 1492 1] Subtable Type : 0F [Generic Interrupt Transl= ator] [5D5h 1493 1] Length : 14 [5D6h 1494 2] Reserved : 0000 [5D8h 1496 4] Translation ID : 00000004 [5DCh 1500 8] Base Address : 0000000030140000 [5E4h 1508 4] Reserved : 00000000 [5E8h 1512 1] Subtable Type : 0F [Generic Interrupt Transl= ator] [5E9h 1513 1] Length : 14 [5EAh 1514 2] Reserved : 0000 [5ECh 1516 4] Translation ID : 00000005 [5F0h 1520 8] Base Address : 0000000030180000 [5F8h 1528 4] Reserved : 00000000 Raw Table Data: Length 1532 (0x5FC) 0000: 41 50 49 43 FC 05 00 00 05 0B 41 52 4D 4C 54 44 // APIC......ARM= LTD 0010: 41 52 4D 53 47 49 20 20 28 07 22 20 41 52 4D 20 // ARMSGI (." A= RM 0020: 99 29 00 00 00 00 00 00 00 00 00 00 0B 50 00 00 // .)...........= P.. 0030: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0040: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0060: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0070: 00 00 00 00 00 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0080: 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0090: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 00B0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 00C0: 00 00 01 00 00 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 00D0: 00 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 00E0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0100: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0110: 00 00 02 00 00 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0120: 00 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0130: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0150: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0160: 00 00 03 00 00 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0170: 00 00 00 00 04 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0180: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 01A0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 01B0: 00 00 00 00 01 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 01C0: 00 00 00 00 05 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 01D0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 01E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 01F0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0200: 00 00 01 00 01 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0210: 00 00 00 00 06 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0220: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0240: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0250: 00 00 02 00 01 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0260: 00 00 00 00 07 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0270: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0290: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 02A0: 00 00 03 00 01 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 02B0: 00 00 00 00 08 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 02C0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 02D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 02E0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 02F0: 00 00 00 00 02 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0300: 00 00 00 00 09 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0310: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0330: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0340: 00 00 01 00 02 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0350: 00 00 00 00 0A 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0360: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0380: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0390: 00 00 02 00 02 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 03A0: 00 00 00 00 0B 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 03B0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 03C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 03D0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 03E0: 00 00 03 00 02 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 03F0: 00 00 00 00 0C 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0400: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0410: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0420: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0430: 00 00 00 00 03 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0440: 00 00 00 00 0D 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0450: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0460: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0470: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0480: 00 00 01 00 03 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 0490: 00 00 00 00 0E 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 04A0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 04B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 04C0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 04D0: 00 00 02 00 03 00 00 00 00 00 00 00 0B 50 00 00 // .............= P.. 04E0: 00 00 00 00 0F 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 04F0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0510: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0520: 00 00 03 00 03 00 00 00 00 00 00 00 0C 18 00 00 // .............= ... 0530: 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 00 // .......0.....= ... 0540: 03 00 00 00 0E 10 00 00 00 00 1C 30 00 00 00 00 // ...........0.= ... 0550: 00 00 00 01 0E 10 00 00 00 00 1C 30 00 04 00 00 // ...........0.= ... 0560: 00 00 00 01 0E 10 00 00 00 00 1C 30 00 08 00 00 // ...........0.= ... 0570: 00 00 00 01 0E 10 00 00 00 00 1C 30 00 0C 00 00 // ...........0.= ... 0580: 00 00 00 01 0F 14 00 00 00 00 00 00 00 00 04 30 // .............= ..0 0590: 00 00 00 00 00 00 00 00 0F 14 00 00 01 00 00 00 // .............= ... 05A0: 00 00 08 30 00 00 00 00 00 00 00 00 0F 14 00 00 // ...0.........= ... 05B0: 02 00 00 00 00 00 0C 30 00 00 00 00 00 00 00 00 // .......0.....= ... 05C0: 0F 14 00 00 03 00 00 00 00 00 10 30 00 00 00 00 // ...........0.= ... 05D0: 00 00 00 00 0F 14 00 00 04 00 00 00 00 00 14 30 // .............= ..0 05E0: 00 00 00 00 00 00 00 00 0F 14 00 00 05 00 00 00 // .............= ... 05F0: 00 00 18 30 00 00 00 00 00 00 00 00 // ...0........ [/snip] [/SAMI] [Nishant] I manually traversed through the code logic with the example given above an= d I think the logic can handle it. Could you please point out the exact problem with the patch? [/Nishant] Please point me to the documentation or code that has a standardised way of= updating the ACPI table. [SAMI] There is a reference implementation at https://github.com/tianocore/= edk2-platforms/blob/master/Platform/ARM/VExpressPkg/ConfigurationManager/Co= nfigurationManagerDxe/ConfigurationManager.c#L475-L487 [Nishant] This expects the GIC structure to be present linearly in the memory. The algorithm implemented in the code is flexible. It checks the ID of each= node present in the table and processes it only if it is of type EFI_ACPI_= 6_4_GIC(0xB). [/Nishant] Regarding the use of the Dynamic Table Framework, there are no short-term p= lans to migrate to it. For the use of dynamic table [/Nishant] + GicStructure =3D (EFI_ACPI_6_4_GIC_STRUCTURE *)StructureListHead; + // Disable the CPU if its MPID is present in the list. + MpidPresent =3D CheckIfMpidIsPresent( + HobData->IsolatedCpuList.Mpid, + HobData->IsolatedCpuList.Count, + GicStructure->MPIDR + ); + if (MpidPresent =3D=3D TRUE) { + DEBUG (( + DEBUG_INFO, + "Disabling Core: %lu, MPID: 0x%llx in MADT\n", + GicStructure->AcpiProcessorUid, + GicStructure->MPIDR + )); + GicStructure->Flags =3D 0; + } + } + + // Second element in the structure component header is length + StructureListHead +=3D StructureListHead[1]; + } +} + +/** + Callback to validate and/or update ACPI table. + + On finding a MADT table, disable the isolated CPUs in the MADT table. Th= e + list of isolated CPUs are obtained from the HOB data. + + @param[in] AcpiHeader Target ACPI table. + + @retval TURE Table validated/updated successfully. + @retval FALSE Error in Table validation/updation. +**/ +STATIC +BOOLEAN +CheckAndUpdateAcpiTable ( + IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader + ) +{ + VOID *SystemIdHob; + SGI_PLATFORM_DESCRIPTOR *HobData; + + // This check updates the MADT table to disable isolated CPUs present on= the + // platform. + if (AcpiHeader->Signature =3D=3D EFI_ACPI_1_0_APIC_SIGNATURE) { [SAMI] Why EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE is not us= ed here? [Nishant] I will update in the next version. + SystemIdHob =3D GetFirstGuidHob (&gArmSgiPlatformIdDescriptorGuid); + if (SystemIdHob !=3D NULL) { + HobData =3D (SGI_PLATFORM_DESCRIPTOR *)GET_GUID_HOB_DATA (SystemIdHo= b); + UpdateMadtTable (AcpiHeader, HobData); + } + } + + return TRUE; +} + EFI_STATUS EFIAPI ArmSgiPkgEntryPoint ( @@ -25,7 +149,10 @@ ArmSgiPkgEntryPoint ( { EFI_STATUS Status; - Status =3D LocateAndInstallAcpiFromFv (&gArmSgiAcpiTablesGuid); + Status =3D LocateAndInstallAcpiFromFvConditional ( + &gArmSgiAcpiTablesGuid, + &CheckAndUpdateAcpiTable + ); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "%a: Failed to install ACPI tables\n", __FUNCTION= __)); return Status; diff --git a/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c b= /Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c index 7df52cc4fd7c..f778dc8ac7c1 100644 --- a/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c +++ b/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018, ARM Limited. All rights reserved. +* Copyright (c) 2018-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -38,6 +38,8 @@ GetSgiSystemId ( CONST VOID *NtFwCfgDtBlob; SGI_NT_FW_CONFIG_INFO_PPI *NtFwConfigInfoPpi; EFI_STATUS Status; + UINT64 IsolatedCpuCount; + UINT64 CoreCount; Status =3D PeiServicesLocatePpi (&gNtFwConfigDtInfoPpiGuid, 0, NULL, (VOID**)&NtFwConfigInfoPpi); @@ -83,6 +85,32 @@ GetSgiSystemId ( HobData->MultiChipMode =3D fdt32_to_cpu (*Property); } + Property =3D fdt_getprop (NtFwCfgDtBlob, Offset, "isolated-cpu-list", NU= LL); + if (Property =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "%s property not found\n", "isolated-cpu-list")); + HobData->IsolatedCpuList.Count =3D 0; + } else { + CopyMem (&IsolatedCpuCount, Property, sizeof (IsolatedCpuCount)); + CoreCount =3D + FixedPcdGet32 (PcdChipCount) * + FixedPcdGet32 (PcdClusterCount) * + FixedPcdGet32 (PcdCoreCount); + if (IsolatedCpuCount > CoreCount) { + DEBUG (( + DEBUG_ERROR, + "IsolatedCpuCount(%u) is higher than CoreCount(%u)\n", + IsolatedCpuCount, + CoreCount + )); + return EFI_SUCCESS; [SAMI] Is the status code returned here correct? Should this be EFI_INVALID= _PARAMETER? Also the function name GetSgiSystemId() seems to no longer refl= ect what the function does. Hace you considered renaming it. [Nishant] This is done intentionally, we want to keep booting even if the config prov= ided is corrupted. I will update the function name in the next version. [/Nishant] + } + CopyMem ( + &HobData->IsolatedCpuList, + Property, + sizeof(HobData->IsolatedCpuList) + (CoreCount * sizeof(UINT64)) [SAMI] Coding convention is not followed here and at other places. Can you = fix, please? [Nishant] Will update in the next patch version. + ); + } + return EFI_SUCCESS; } @@ -104,11 +132,24 @@ SgiPlatformPeim ( { SGI_PLATFORM_DESCRIPTOR *HobData; EFI_STATUS Status; + UINT64 CoreCount; + UINTN HobSize; + CoreCount =3D + FixedPcdGet32 (PcdChipCount) * + FixedPcdGet32 (PcdClusterCount) * + FixedPcdGet32 (PcdCoreCount); + + // Additional size for SGI_ISOLATED_CPU_LIST. + // Size =3D (MPID register size in bytes * CoreCount) + + // sizeof(SGI_PLATFORM_DESCRIPTOR) + HobSize =3D + sizeof (SGI_PLATFORM_DESCRIPTOR) + + (CoreCount * sizeof(UINT64)); // Create platform descriptor HOB HobData =3D (SGI_PLATFORM_DESCRIPTOR *)BuildGuidHob ( &gArmSgiPlatformIdDescriptorGuid, - sizeof (SGI_PLATFORM_DESCRIPTOR))= ; + HobSize); // Get the system id from the platform specific nt_fw_config device tree if (HobData =3D=3D NULL) { IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you. IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you. --_000_AS4PR08MB80477A3F065666B4AEFD781E86649AS4PR08MB8047eurp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Hey Sami,

This code is shared between all the variants of the Sgi platform.
Depending upon the variant, there will be a different number of CPUs presen= t on it. To handle this I have written the code in a generic way.

The Dsdt containing AML code describing Cluster topology does not have any = field for CPU state.
AFAIK, the MADT table is used to check if the CPU is enabled and to get its= MPID number.
I have tested this code and cat /proc/cpuinfo does not show disabled CPUs i= n the list.

linux/processor_core.c at mas= ter =B7 torvalds/linux (github.com) this is the code that maps the= logical id to the MPID number.

Regards,
Nishant

From: Sami Mujawar <Sami= .Mujawar@arm.com>
Sent: Monday, August 8, 2022 10:11 AM
To: Nishant Sharma <Nishant.Sharma@arm.com>; devel@edk2.groups= .io <devel@edk2.groups.io>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH 1/1] Platform/Sgi:= Add support to disable isolated cpus
 

Hi Nishant,

 

The parsing code would be much clear if you define a GIC s= ubstructure header (if not already present) and then traverse the data.

To add to this your patch does not address the AML code wh= ich still says that the CPU is enabled. You would need to update the AML co= de in this patch otherwise you end up having inconsistent view of the CPU s= tate.

 

Regards,

 

Sami Mujawar

 

 

From: Nishant Sharma <nishant.sharma@arm.= com>
Date: Friday, 5 August 2022 at 12:19
To: Sami Mujawar <Sami.Mujawar@arm.com>, "devel@edk2.grou= ps.io" <devel@edk2.groups.io>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH 1/1] Platform/Sgi:= Add support to disable isolated cpus

 

Hi Sami,

Please find my response inline

On Thu, Jul 28, 2022 at 06:12 PM, Sami Mujawar wrote:

Hi Nishant,

Please find my response inline marked [SAMI].

Regards,

Sami Mujawar

On 27/07/2022 02:53 pm, Nishant Sharma wrote:

Hi Sami,
Please find my reply inline

On Thu, Jul 21, 2022 at 12:47 PM, Sami Mujawar wrote:

Hi Nishant,

Please find my response inline marked [SAMI].

Regards,

Sami Mujawar

On 17/06/2022 07:07 am, Nishant Sharma wrote:

Isolated CPUs are those that are not to be used on the platform for=

various reasons. The isolated CPU list is an array of MPID values o=
f

[SAMI] Can you explain the use-case/reason, please?

[Nishant]: I will update in the next patchset.

the CPUs that have to be isolated. This list is supplied via the

NT_FW_CONFIG dtb.


 


Add support to search for isolated CPUs MPID list and, if present,<=
/pre>

update the MADT table to disable the corresponding CPUs.


 


Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>


---


 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf  &=
nbsp;      |   1 -


 Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf |&nb=
sp;  8 +-


 Platform/ARM/SgiPkg/Include/SgiPlatform.h    &=
nbsp;           &nbs=
p;    |   7 ++


 Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c  &=
nbsp;      | 131 +++++++++++++++++++-


 Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c =
 |  45 ++++++-


 5 files changed, 186 insertions(+), 6 deletions(-)


 


diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf =
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf


index 4b36c3e5ceb2..e13c2f08ce6e 100644


--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf


+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf


@@ -18,7 +18,6 @@


   Dbg2.aslc


 


   Fadt.aslc


 


   Gtdt.aslc


 


-  Iort.aslc

[SAMI] Why is IORT table being removed here?

[Nishant]: I think some issue with patch generation. I will remove this cha= nge in the next patch. Thanks for pointing it out.

   Mcfg.aslc
 
   RdN2Cfg1/Dsdt.asl
 
   RdN2Cfg1/Madt.aslc
 
diff --git a/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatform=
Pei.inf b/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf

index 407160c07563..fbf061ad3bdb 100644


--- a/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf=



+++ b/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPei.inf=



@@ -1,5 +1,5 @@


 #


 


-#  Copyright (c) 2018, ARM Limited. All rights reserved.

 


+#  Copyright (c) 2018-2022, ARM Limited. All rights reserved.=



 


 #


 


 #  SPDX-License-Identifier: BSD-2-Clause-Patent


 


 #


 


@@ -13,6 +13,7 @@


   ENTRY_POINT       &=
nbsp;            =3D=
 SgiPlatformPeim


 


 


 


 [Packages]


 


+  ArmPlatformPkg/ArmPlatformPkg.dec


 


   EmbeddedPkg/EmbeddedPkg.dec


 


   MdePkg/MdePkg.dec


 


   Platform/ARM/SgiPkg/SgiPlatform.dec


 


@@ -21,6 +22,11 @@


   FdtLib


 


   PeimEntryPoint


 


 


 


+[FixedPcd]


 


+  gArmSgiTokenSpaceGuid.PcdChipCount


 


+  gArmPlatformTokenSpaceGuid.PcdCoreCount


 


+  gArmPlatformTokenSpaceGuid.PcdClusterCount


 


+


 


 [Sources]


 


   SgiPlatformPeim.c


 


 


 


diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/A=
RM/SgiPkg/Include/SgiPlatform.h


index dddb58832d73..311286ce5337 100644


--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h


+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h


@@ -65,11 +65,18 @@


 #define DRAM_BLOCK2_BASE_REMOTE(ChipId) \


 


           (SGI_R=
EMOTE_CHIP_MEM_OFFSET (ChipId) + FixedPcdGet64 (PcdDramBlock2Base))


 


 


 


+// List of isolated CPUs MPID


 


+typedef struct {


 


+  UINT64  Count;      &nbs=
p;         // Number of elements pr=
esent in the list


 


+  UINT64  Mpid[];      &nb=
sp;        // List containing isolated C=
PU MPIDs


 


+} SGI_ISOLATED_CPU_LIST;


 


+


 


 // ARM platform description data.


 


 typedef struct {


 


   UINTN  PlatformId;


 


   UINTN  ConfigId;


 


   UINTN  MultiChipMode;


 


+  SGI_ISOLATED_CPU_LIST  IsolatedCpuList;


 


 } SGI_PLATFORM_DESCRIPTOR;


 


 


 


 // Arm SGI/RD Product IDs


 


diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c =
b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c


index 2f72e7152ff3..80190120ff32 100644


--- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c


+++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c


@@ -1,14 +1,17 @@


 /** @file


 


 *


 


-*  Copyright (c) 2018, ARM Limited. All rights reserved.

 


+*  Copyright (c) 2018 - 2022, ARM Limited. All rights reserve=
d.


 


 *


 


 *  SPDX-License-Identifier: BSD-2-Clause-Patent


 


 *


 


 **/


 


 


 


+#include <IndustryStandard/Acpi.h>


 


+


 


 #include <Library/AcpiLib.h>


 


 #include <Library/DebugLib.h>


 


 #include <Library/HobLib.h>


 


+#include <Library/UefiBootServicesTableLib.h>


 


 #include <SgiPlatform.h>


 


 


 


 VOID


 


@@ -16,6 +19,127 @@ InitVirtioDevices (


   VOID


 


   );


 


 


 


+/**


 


+  Search for a MPID in a list


 


+


 


+  Performs a linear search for a specified MPID on the given =
linear


 


+  list of MPIDs.


 


+


 


+  @param[in]  MpidList  Pointer to list.


 


+  @param[in]  Count     Number of th=
e elements in the list.


 


+  @param[in]  Mpid      Target =
MPID.


 


+


 


+  @retval TRUE   MPID is present.


 


+  @retval FALSE  MPID is not present.


 


+**/


 


+STATIC


 


+BOOLEAN


 


+CheckIfMpidIsPresent (


 


+  IN UINT64  *MpidList,


 


+  IN UINT64  Count,


 


+  IN UINT64  Mpid


 


+  )


 


+{


 


+  UINT64 Idx;


 


+


 


+  for (Idx =3D 0; Idx < Count; Idx++) {


 


+    if (MpidList[Idx] =3D=3D Mpid) {


 


+      return TRUE;


 


+    }


 


+  }


 


+


 


+  return FALSE;


 


+}


 


+


 


+/**


 


+  Disables isolated CPUs in the MADT table


 


+


 


+  Parse the IsolatedCpuInfo from the Hob list and updates the=
 MADT table to

[SAMI] Nit.  updates -> update

[Nishant] Will update in next patch version.

+  disable cpu's which are not available on the platfrom.

 


+


 


+  @param[in] AcpiHeader  Points to the Madt table.


 


+  @param[in] HobData     Points to the un=
usable cpuinfo in hoblist.


 


+**/


 


+STATIC


 


+VOID


 


+UpdateMadtTable (


 


+  IN EFI_ACPI_DESCRIPTION_HEADER  *AcpiHeader,


 


+  IN SGI_PLATFORM_DESCRIPTOR      *H=
obData


 


+  )


 


+{


 


+  UINT8 *StructureListHead;


 


+  UINT8 *StructureListTail;


 


+  EFI_ACPI_6_4_GIC_STRUCTURE *GicStructure;


 


+  BOOLEAN MpidPresent;


 


+


 


+  if (HobData->IsolatedCpuList.Count =3D=3D 0) {


 


+    return;


 


+  }


 


+


 


+  StructureListHead =3D


 


+    ((UINT8 *)AcpiHeader) +


 


+    sizeof(EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_T=
ABLE_HEADER);


 


+  StructureListTail =3D (UINT8 *)AcpiHeader + AcpiHeader->=
Length;


 


+


 


+  // Locate ACPI GICC structure in the MADT table.


 


+  while (StructureListHead < StructureListTail) {


 


+    if (StructureListHead[0] =3D=3D EFI_ACPI_6_4_GI=
C) {

[SAMI] This is definitely not the way to parse an ACPI table. Please don= t do this.

Also, why are you not using DynamicTables framework? It is designed to h= andle such cases.

[/SAMI]

[Nishant]
Could you please add more details on what is wrong with this approach?

[SAMI] The problem is it does not work with the ACPI table below:

[snip]

/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20210930 (32-bit version)
 * Copyright (c) 2000 - 2021 Intel Corporation
 *
 * Disassembly of apic0000.bin, Thu Jul 28 17:57:00 2022
 *
 * ACPI Data Table [APIC]
 *
 * Format: [HexOffset DecimalOffset ByteLength]  FieldName : Fiel= dValue (in hex)
 */

[000h 0000   4]        &n= bsp;           Signature = : "APIC"    [Multiple APIC Description Table (MADT= )]
[004h 0004   4]        &n= bsp;        Table Length : 000005FC
[008h 0008   1]        &n= bsp;            Revi= sion : 05
[009h 0009   1]        &n= bsp;            Chec= ksum : 0B
[00Ah 0010   6]        &n= bsp;            = ;  Oem ID : "ARMLTD"
[010h 0016   8]        &n= bsp;        Oem Table ID : "ARMSGI&= nbsp; "
[018h 0024   4]        &n= bsp;        Oem Revision : 20220728
[01Ch 0028   4]        &n= bsp;     Asl Compiler ID : "ARM "
[020h 0032   4]        Asl Com= piler Revision : 00002999

[024h 0036   4]        &n= bsp;  Local Apic Address : 00000000
[028h 0040   4]        Flags (= decoded below) : 00000000
            &nb= sp;            PC-AT= Compatibility : 0

[02Ch 0044   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[02Dh 0045   1]        &n= bsp;            = ;  Length : 50
[02Eh 0046   2]        &n= bsp;            Rese= rved : 0000
[030h 0048   4]         C= PU Interface Number : 00000000
[034h 0052   4]        &n= bsp;       Processor UID : 00000000
[038h 0056   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[03Ch 0060   4]     Parking Protocol Version = : 00000000
[040h 0064   4]        Perform= ance Interrupt : 00000017
[044h 0068   8]        &n= bsp;      Parked Address : 0000000000000000
[04Ch 0076   8]        &n= bsp;        Base Address : 0000000000000= 000
[054h 0084   8]     Virtual GIC Base Address = : 0000000000000000
[05Ch 0092   8]  Hypervisor GIC Base Address : 0000000000000= 000
[064h 0100   4]        Virtual= GIC Interrupt : 00000019
[068h 0104   8]   Redistributor Base Address : 00000000= 00000000
[070h 0112   8]        &n= bsp;           ARM MPIDR = : 0000000000000000
[078h 0120   1]        &n= bsp;    Efficiency Class : 00
[079h 0121   1]        &n= bsp;            Rese= rved : 00
[07Ah 0122   2]       SPE Overflow = Interrupt : 0000

[07Ch 0124   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[07Dh 0125   1]        &n= bsp;            = ;  Length : 50
[07Eh 0126   2]        &n= bsp;            Rese= rved : 0000
[080h 0128   4]         C= PU Interface Number : 00000000
[084h 0132   4]        &n= bsp;       Processor UID : 00000001
[088h 0136   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[08Ch 0140   4]     Parking Protocol Version = : 00000000
[090h 0144   4]        Perform= ance Interrupt : 00000017
[094h 0148   8]        &n= bsp;      Parked Address : 0000000000000000
[09Ch 0156   8]        &n= bsp;        Base Address : 0000000000000= 000
[0A4h 0164   8]     Virtual GIC Base Address = : 0000000000000000
[0ACh 0172   8]  Hypervisor GIC Base Address : 0000000000000= 000
[0B4h 0180   4]        Virtual= GIC Interrupt : 00000019
[0B8h 0184   8]   Redistributor Base Address : 00000000= 00000000
[0C0h 0192   8]        &n= bsp;           ARM MPIDR = : 0000000000010000
[0C8h 0200   1]        &n= bsp;    Efficiency Class : 00
[0C9h 0201   1]        &n= bsp;            Rese= rved : 00
[0CAh 0202   2]       SPE Overflow = Interrupt : 0000

[0CCh 0204   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[0CDh 0205   1]        &n= bsp;            = ;  Length : 50
[0CEh 0206   2]        &n= bsp;            Rese= rved : 0000
[0D0h 0208   4]         C= PU Interface Number : 00000000
[0D4h 0212   4]        &n= bsp;       Processor UID : 00000002
[0D8h 0216   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[0DCh 0220   4]     Parking Protocol Version = : 00000000
[0E0h 0224   4]        Perform= ance Interrupt : 00000017
[0E4h 0228   8]        &n= bsp;      Parked Address : 0000000000000000
[0ECh 0236   8]        &n= bsp;        Base Address : 0000000000000= 000
[0F4h 0244   8]     Virtual GIC Base Address = : 0000000000000000
[0FCh 0252   8]  Hypervisor GIC Base Address : 0000000000000= 000
[104h 0260   4]        Virtual= GIC Interrupt : 00000019
[108h 0264   8]   Redistributor Base Address : 00000000= 00000000
[110h 0272   8]        &n= bsp;           ARM MPIDR = : 0000000000020000
[118h 0280   1]        &n= bsp;    Efficiency Class : 00
[119h 0281   1]        &n= bsp;            Rese= rved : 00
[11Ah 0282   2]       SPE Overflow = Interrupt : 0000

[11Ch 0284   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[11Dh 0285   1]        &n= bsp;            = ;  Length : 50
[11Eh 0286   2]        &n= bsp;            Rese= rved : 0000
[120h 0288   4]         C= PU Interface Number : 00000000
[124h 0292   4]        &n= bsp;       Processor UID : 00000003
[128h 0296   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[12Ch 0300   4]     Parking Protocol Version = : 00000000
[130h 0304   4]        Perform= ance Interrupt : 00000017
[134h 0308   8]        &n= bsp;      Parked Address : 0000000000000000
[13Ch 0316   8]        &n= bsp;        Base Address : 0000000000000= 000
[144h 0324   8]     Virtual GIC Base Address = : 0000000000000000
[14Ch 0332   8]  Hypervisor GIC Base Address : 0000000000000= 000
[154h 0340   4]        Virtual= GIC Interrupt : 00000019
[158h 0344   8]   Redistributor Base Address : 00000000= 00000000
[160h 0352   8]        &n= bsp;           ARM MPIDR = : 0000000000030000
[168h 0360   1]        &n= bsp;    Efficiency Class : 00
[169h 0361   1]        &n= bsp;            Rese= rved : 00
[16Ah 0362   2]       SPE Overflow = Interrupt : 0000

[16Ch 0364   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[16Dh 0365   1]        &n= bsp;            = ;  Length : 50
[16Eh 0366   2]        &n= bsp;            Rese= rved : 0000
[170h 0368   4]         C= PU Interface Number : 00000000
[174h 0372   4]        &n= bsp;       Processor UID : 00000004
[178h 0376   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[17Ch 0380   4]     Parking Protocol Version = : 00000000
[180h 0384   4]        Perform= ance Interrupt : 00000017
[184h 0388   8]        &n= bsp;      Parked Address : 0000000000000000
[18Ch 0396   8]        &n= bsp;        Base Address : 0000000000000= 000
[194h 0404   8]     Virtual GIC Base Address = : 0000000000000000
[19Ch 0412   8]  Hypervisor GIC Base Address : 0000000000000= 000
[1A4h 0420   4]        Virtual= GIC Interrupt : 00000019
[1A8h 0424   8]   Redistributor Base Address : 00000000= 00000000
[1B0h 0432   8]        &n= bsp;           ARM MPIDR = : 0000000100000000
[1B8h 0440   1]        &n= bsp;    Efficiency Class : 00
[1B9h 0441   1]        &n= bsp;            Rese= rved : 00
[1BAh 0442   2]       SPE Overflow = Interrupt : 0000

[1BCh 0444   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[1BDh 0445   1]        &n= bsp;            = ;  Length : 50
[1BEh 0446   2]        &n= bsp;            Rese= rved : 0000
[1C0h 0448   4]         C= PU Interface Number : 00000000
[1C4h 0452   4]        &n= bsp;       Processor UID : 00000005
[1C8h 0456   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[1CCh 0460   4]     Parking Protocol Version = : 00000000
[1D0h 0464   4]        Perform= ance Interrupt : 00000017
[1D4h 0468   8]        &n= bsp;      Parked Address : 0000000000000000
[1DCh 0476   8]        &n= bsp;        Base Address : 0000000000000= 000
[1E4h 0484   8]     Virtual GIC Base Address = : 0000000000000000
[1ECh 0492   8]  Hypervisor GIC Base Address : 0000000000000= 000
[1F4h 0500   4]        Virtual= GIC Interrupt : 00000019
[1F8h 0504   8]   Redistributor Base Address : 00000000= 00000000
[200h 0512   8]        &n= bsp;           ARM MPIDR = : 0000000100010000
[208h 0520   1]        &n= bsp;    Efficiency Class : 00
[209h 0521   1]        &n= bsp;            Rese= rved : 00
[20Ah 0522   2]       SPE Overflow = Interrupt : 0000

[20Ch 0524   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[20Dh 0525   1]        &n= bsp;            = ;  Length : 50
[20Eh 0526   2]        &n= bsp;            Rese= rved : 0000
[210h 0528   4]         C= PU Interface Number : 00000000
[214h 0532   4]        &n= bsp;       Processor UID : 00000006
[218h 0536   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[21Ch 0540   4]     Parking Protocol Version = : 00000000
[220h 0544   4]        Perform= ance Interrupt : 00000017
[224h 0548   8]        &n= bsp;      Parked Address : 0000000000000000
[22Ch 0556   8]        &n= bsp;        Base Address : 0000000000000= 000
[234h 0564   8]     Virtual GIC Base Address = : 0000000000000000
[23Ch 0572   8]  Hypervisor GIC Base Address : 0000000000000= 000
[244h 0580   4]        Virtual= GIC Interrupt : 00000019
[248h 0584   8]   Redistributor Base Address : 00000000= 00000000
[250h 0592   8]        &n= bsp;           ARM MPIDR = : 0000000100020000
[258h 0600   1]        &n= bsp;    Efficiency Class : 00
[259h 0601   1]        &n= bsp;            Rese= rved : 00
[25Ah 0602   2]       SPE Overflow = Interrupt : 0000

[25Ch 0604   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[25Dh 0605   1]        &n= bsp;            = ;  Length : 50
[25Eh 0606   2]        &n= bsp;            Rese= rved : 0000
[260h 0608   4]         C= PU Interface Number : 00000000
[264h 0612   4]        &n= bsp;       Processor UID : 00000007
[268h 0616   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[26Ch 0620   4]     Parking Protocol Version = : 00000000
[270h 0624   4]        Perform= ance Interrupt : 00000017
[274h 0628   8]        &n= bsp;      Parked Address : 0000000000000000
[27Ch 0636   8]        &n= bsp;        Base Address : 0000000000000= 000
[284h 0644   8]     Virtual GIC Base Address = : 0000000000000000
[28Ch 0652   8]  Hypervisor GIC Base Address : 0000000000000= 000
[294h 0660   4]        Virtual= GIC Interrupt : 00000019
[298h 0664   8]   Redistributor Base Address : 00000000= 00000000
[2A0h 0672   8]        &n= bsp;           ARM MPIDR = : 0000000100030000
[2A8h 0680   1]        &n= bsp;    Efficiency Class : 00
[2A9h 0681   1]        &n= bsp;            Rese= rved : 00
[2AAh 0682   2]       SPE Overflow = Interrupt : 0000

[2ACh 0684   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[2ADh 0685   1]        &n= bsp;            = ;  Length : 50
[2AEh 0686   2]        &n= bsp;            Rese= rved : 0000
[2B0h 0688   4]         C= PU Interface Number : 00000000
[2B4h 0692   4]        &n= bsp;       Processor UID : 00000008
[2B8h 0696   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[2BCh 0700   4]     Parking Protocol Version = : 00000000
[2C0h 0704   4]        Perform= ance Interrupt : 00000017
[2C4h 0708   8]        &n= bsp;      Parked Address : 0000000000000000
[2CCh 0716   8]        &n= bsp;        Base Address : 0000000000000= 000
[2D4h 0724   8]     Virtual GIC Base Address = : 0000000000000000
[2DCh 0732   8]  Hypervisor GIC Base Address : 0000000000000= 000
[2E4h 0740   4]        Virtual= GIC Interrupt : 00000019
[2E8h 0744   8]   Redistributor Base Address : 00000000= 00000000
[2F0h 0752   8]        &n= bsp;           ARM MPIDR = : 0000000200000000
[2F8h 0760   1]        &n= bsp;    Efficiency Class : 00
[2F9h 0761   1]        &n= bsp;            Rese= rved : 00
[2FAh 0762   2]       SPE Overflow = Interrupt : 0000

[2FCh 0764   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[2FDh 0765   1]        &n= bsp;            = ;  Length : 50
[2FEh 0766   2]        &n= bsp;            Rese= rved : 0000
[300h 0768   4]         C= PU Interface Number : 00000000
[304h 0772   4]        &n= bsp;       Processor UID : 00000009
[308h 0776   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[30Ch 0780   4]     Parking Protocol Version = : 00000000
[310h 0784   4]        Perform= ance Interrupt : 00000017
[314h 0788   8]        &n= bsp;      Parked Address : 0000000000000000
[31Ch 0796   8]        &n= bsp;        Base Address : 0000000000000= 000
[324h 0804   8]     Virtual GIC Base Address = : 0000000000000000
[32Ch 0812   8]  Hypervisor GIC Base Address : 0000000000000= 000
[334h 0820   4]        Virtual= GIC Interrupt : 00000019
[338h 0824   8]   Redistributor Base Address : 00000000= 00000000
[340h 0832   8]        &n= bsp;           ARM MPIDR = : 0000000200010000
[348h 0840   1]        &n= bsp;    Efficiency Class : 00
[349h 0841   1]        &n= bsp;            Rese= rved : 00
[34Ah 0842   2]       SPE Overflow = Interrupt : 0000

[34Ch 0844   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[34Dh 0845   1]        &n= bsp;            = ;  Length : 50
[34Eh 0846   2]        &n= bsp;            Rese= rved : 0000
[350h 0848   4]         C= PU Interface Number : 00000000
[354h 0852   4]        &n= bsp;       Processor UID : 0000000A
[358h 0856   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[35Ch 0860   4]     Parking Protocol Version = : 00000000
[360h 0864   4]        Perform= ance Interrupt : 00000017
[364h 0868   8]        &n= bsp;      Parked Address : 0000000000000000
[36Ch 0876   8]        &n= bsp;        Base Address : 0000000000000= 000
[374h 0884   8]     Virtual GIC Base Address = : 0000000000000000
[37Ch 0892   8]  Hypervisor GIC Base Address : 0000000000000= 000
[384h 0900   4]        Virtual= GIC Interrupt : 00000019
[388h 0904   8]   Redistributor Base Address : 00000000= 00000000
[390h 0912   8]        &n= bsp;           ARM MPIDR = : 0000000200020000
[398h 0920   1]        &n= bsp;    Efficiency Class : 00
[399h 0921   1]        &n= bsp;            Rese= rved : 00
[39Ah 0922   2]       SPE Overflow = Interrupt : 0000

[39Ch 0924   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[39Dh 0925   1]        &n= bsp;            = ;  Length : 50
[39Eh 0926   2]        &n= bsp;            Rese= rved : 0000
[3A0h 0928   4]         C= PU Interface Number : 00000000
[3A4h 0932   4]        &n= bsp;       Processor UID : 0000000B
[3A8h 0936   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[3ACh 0940   4]     Parking Protocol Version = : 00000000
[3B0h 0944   4]        Perform= ance Interrupt : 00000017
[3B4h 0948   8]        &n= bsp;      Parked Address : 0000000000000000
[3BCh 0956   8]        &n= bsp;        Base Address : 0000000000000= 000
[3C4h 0964   8]     Virtual GIC Base Address = : 0000000000000000
[3CCh 0972   8]  Hypervisor GIC Base Address : 0000000000000= 000
[3D4h 0980   4]        Virtual= GIC Interrupt : 00000019
[3D8h 0984   8]   Redistributor Base Address : 00000000= 00000000
[3E0h 0992   8]        &n= bsp;           ARM MPIDR = : 0000000200030000
[3E8h 1000   1]        &n= bsp;    Efficiency Class : 00
[3E9h 1001   1]        &n= bsp;            Rese= rved : 00
[3EAh 1002   2]       SPE Overflow = Interrupt : 0000

[3ECh 1004   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[3EDh 1005   1]        &n= bsp;            = ;  Length : 50
[3EEh 1006   2]        &n= bsp;            Rese= rved : 0000
[3F0h 1008   4]         C= PU Interface Number : 00000000
[3F4h 1012   4]        &n= bsp;       Processor UID : 0000000C
[3F8h 1016   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[3FCh 1020   4]     Parking Protocol Version = : 00000000
[400h 1024   4]        Perform= ance Interrupt : 00000017
[404h 1028   8]        &n= bsp;      Parked Address : 0000000000000000
[40Ch 1036   8]        &n= bsp;        Base Address : 0000000000000= 000
[414h 1044   8]     Virtual GIC Base Address = : 0000000000000000
[41Ch 1052   8]  Hypervisor GIC Base Address : 0000000000000= 000
[424h 1060   4]        Virtual= GIC Interrupt : 00000019
[428h 1064   8]   Redistributor Base Address : 00000000= 00000000
[430h 1072   8]        &n= bsp;           ARM MPIDR = : 0000000300000000
[438h 1080   1]        &n= bsp;    Efficiency Class : 00
[439h 1081   1]        &n= bsp;            Rese= rved : 00
[43Ah 1082   2]       SPE Overflow = Interrupt : 0000

[43Ch 1084   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[43Dh 1085   1]        &n= bsp;            = ;  Length : 50
[43Eh 1086   2]        &n= bsp;            Rese= rved : 0000
[440h 1088   4]         C= PU Interface Number : 00000000
[444h 1092   4]        &n= bsp;       Processor UID : 0000000D
[448h 1096   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[44Ch 1100   4]     Parking Protocol Version = : 00000000
[450h 1104   4]        Perform= ance Interrupt : 00000017
[454h 1108   8]        &n= bsp;      Parked Address : 0000000000000000
[45Ch 1116   8]        &n= bsp;        Base Address : 0000000000000= 000
[464h 1124   8]     Virtual GIC Base Address = : 0000000000000000
[46Ch 1132   8]  Hypervisor GIC Base Address : 0000000000000= 000
[474h 1140   4]        Virtual= GIC Interrupt : 00000019
[478h 1144   8]   Redistributor Base Address : 00000000= 00000000
[480h 1152   8]        &n= bsp;           ARM MPIDR = : 0000000300010000
[488h 1160   1]        &n= bsp;    Efficiency Class : 00
[489h 1161   1]        &n= bsp;            Rese= rved : 00
[48Ah 1162   2]       SPE Overflow = Interrupt : 0000

[48Ch 1164   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[48Dh 1165   1]        &n= bsp;            = ;  Length : 50
[48Eh 1166   2]        &n= bsp;            Rese= rved : 0000
[490h 1168   4]         C= PU Interface Number : 00000000
[494h 1172   4]        &n= bsp;       Processor UID : 0000000E
[498h 1176   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[49Ch 1180   4]     Parking Protocol Version = : 00000000
[4A0h 1184   4]        Perform= ance Interrupt : 00000017
[4A4h 1188   8]        &n= bsp;      Parked Address : 0000000000000000
[4ACh 1196   8]        &n= bsp;        Base Address : 0000000000000= 000
[4B4h 1204   8]     Virtual GIC Base Address = : 0000000000000000
[4BCh 1212   8]  Hypervisor GIC Base Address : 0000000000000= 000
[4C4h 1220   4]        Virtual= GIC Interrupt : 00000019
[4C8h 1224   8]   Redistributor Base Address : 00000000= 00000000
[4D0h 1232   8]        &n= bsp;           ARM MPIDR = : 0000000300020000
[4D8h 1240   1]        &n= bsp;    Efficiency Class : 00
[4D9h 1241   1]        &n= bsp;            Rese= rved : 00
[4DAh 1242   2]       SPE Overflow = Interrupt : 0000

[4DCh 1244   1]        &n= bsp;       Subtable Type : 0B [Generic Interr= upt Controller]
[4DDh 1245   1]        &n= bsp;            = ;  Length : 50
[4DEh 1246   2]        &n= bsp;            Rese= rved : 0000
[4E0h 1248   4]         C= PU Interface Number : 00000000
[4E4h 1252   4]        &n= bsp;       Processor UID : 0000000F
[4E8h 1256   4]        Flags (= decoded below) : 00000001
            &nb= sp;            =   Processor Enabled : 1
          Performance Interrup= t Trigger Mode : 0
          Virtual GIC Interrup= t Trigger Mode : 0
[4ECh 1260   4]     Parking Protocol Version = : 00000000
[4F0h 1264   4]        Perform= ance Interrupt : 00000017
[4F4h 1268   8]        &n= bsp;      Parked Address : 0000000000000000
[4FCh 1276   8]        &n= bsp;        Base Address : 0000000000000= 000
[504h 1284   8]     Virtual GIC Base Address = : 0000000000000000
[50Ch 1292   8]  Hypervisor GIC Base Address : 0000000000000= 000
[514h 1300   4]        Virtual= GIC Interrupt : 00000019
[518h 1304   8]   Redistributor Base Address : 00000000= 00000000
[520h 1312   8]        &n= bsp;           ARM MPIDR = : 0000000300030000
[528h 1320   1]        &n= bsp;    Efficiency Class : 00
[529h 1321   1]        &n= bsp;            Rese= rved : 00
[52Ah 1322   2]       SPE Overflow = Interrupt : 0000

[52Ch 1324   1]        &n= bsp;       Subtable Type : 0C [Generic Interr= upt Distributor]
[52Dh 1325   1]        &n= bsp;            = ;  Length : 18
[52Eh 1326   2]        &n= bsp;            Rese= rved : 0000
[530h 1328   4]        Local G= IC Hardware ID : 00000000
[534h 1332   8]        &n= bsp;        Base Address : 0000000030000= 000
[53Ch 1340   4]        &n= bsp;      Interrupt Base : 00000000
[540h 1344   1]        &n= bsp;            = ; Version : 03
[541h 1345   3]        &n= bsp;            Rese= rved : 000000

[544h 1348   1]        &n= bsp;       Subtable Type : 0E [Generic Interr= upt Redistributor]
[545h 1349   1]        &n= bsp;            = ;  Length : 10
[546h 1350   2]        &n= bsp;            Rese= rved : 0000
[548h 1352   8]        &n= bsp;        Base Address : 00000000301C0= 000
[550h 1360   4]        &n= bsp;            = ;  Length : 01000000

[554h 1364   1]        &n= bsp;       Subtable Type : 0E [Generic Interr= upt Redistributor]
[555h 1365   1]        &n= bsp;            = ;  Length : 10
[556h 1366   2]        &n= bsp;            Rese= rved : 0000
[558h 1368   8]        &n= bsp;        Base Address : 00000400301C0= 000
[560h 1376   4]        &n= bsp;            = ;  Length : 01000000

[564h 1380   1]        &n= bsp;       Subtable Type : 0E [Generic Interr= upt Redistributor]
[565h 1381   1]        &n= bsp;            = ;  Length : 10
[566h 1382   2]        &n= bsp;            Rese= rved : 0000
[568h 1384   8]        &n= bsp;        Base Address : 00000800301C0= 000
[570h 1392   4]        &n= bsp;            = ;  Length : 01000000

[574h 1396   1]        &n= bsp;       Subtable Type : 0E [Generic Interr= upt Redistributor]
[575h 1397   1]        &n= bsp;            = ;  Length : 10
[576h 1398   2]        &n= bsp;            Rese= rved : 0000
[578h 1400   8]        &n= bsp;        Base Address : 00000C00301C0= 000
[580h 1408   4]        &n= bsp;            = ;  Length : 01000000

[584h 1412   1]        &n= bsp;       Subtable Type : 0F [Generic Interr= upt Translator]
[585h 1413   1]        &n= bsp;            = ;  Length : 14
[586h 1414   2]        &n= bsp;            Rese= rved : 0000
[588h 1416   4]        &n= bsp;      Translation ID : 00000000
[58Ch 1420   8]        &n= bsp;        Base Address : 0000000030040= 000
[594h 1428   4]        &n= bsp;            Rese= rved : 00000000

[598h 1432   1]        &n= bsp;       Subtable Type : 0F [Generic Interr= upt Translator]
[599h 1433   1]        &n= bsp;            = ;  Length : 14
[59Ah 1434   2]        &n= bsp;            Rese= rved : 0000
[59Ch 1436   4]        &n= bsp;      Translation ID : 00000001
[5A0h 1440   8]        &n= bsp;        Base Address : 0000000030080= 000
[5A8h 1448   4]        &n= bsp;            Rese= rved : 00000000

[5ACh 1452   1]        &n= bsp;       Subtable Type : 0F [Generic Interr= upt Translator]
[5ADh 1453   1]        &n= bsp;            = ;  Length : 14
[5AEh 1454   2]        &n= bsp;            Rese= rved : 0000
[5B0h 1456   4]        &n= bsp;      Translation ID : 00000002
[5B4h 1460   8]        &n= bsp;        Base Address : 00000000300C0= 000
[5BCh 1468   4]        &n= bsp;            Rese= rved : 00000000

[5C0h 1472   1]        &n= bsp;       Subtable Type : 0F [Generic Interr= upt Translator]
[5C1h 1473   1]        &n= bsp;            = ;  Length : 14
[5C2h 1474   2]        &n= bsp;            Rese= rved : 0000
[5C4h 1476   4]        &n= bsp;      Translation ID : 00000003
[5C8h 1480   8]        &n= bsp;        Base Address : 0000000030100= 000
[5D0h 1488   4]        &n= bsp;            Rese= rved : 00000000

[5D4h 1492   1]        &n= bsp;       Subtable Type : 0F [Generic Interr= upt Translator]
[5D5h 1493   1]        &n= bsp;            = ;  Length : 14
[5D6h 1494   2]        &n= bsp;            Rese= rved : 0000
[5D8h 1496   4]        &n= bsp;      Translation ID : 00000004
[5DCh 1500   8]        &n= bsp;        Base Address : 0000000030140= 000
[5E4h 1508   4]        &n= bsp;            Rese= rved : 00000000

[5E8h 1512   1]        &n= bsp;       Subtable Type : 0F [Generic Interr= upt Translator]
[5E9h 1513   1]        &n= bsp;            = ;  Length : 14
[5EAh 1514   2]        &n= bsp;            Rese= rved : 0000
[5ECh 1516   4]        &n= bsp;      Translation ID : 00000005
[5F0h 1520   8]        &n= bsp;        Base Address : 0000000030180= 000
[5F8h 1528   4]        &n= bsp;            Rese= rved : 00000000

Raw Table Data: Length 1532 (0x5FC)

    0000: 41 50 49 43 FC 05 00 00 05 0B 41 52 4D 4C 54 44&nb= sp; // APIC......ARMLTD
    0010: 41 52 4D 53 47 49 20 20 28 07 22 20 41 52 4D 20&nb= sp; // ARMSGI  (." ARM
    0020: 99 29 00 00 00 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .)...........P..
    0030: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0040: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0060: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0070: 00 00 00 00 00 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0080: 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0090: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    00B0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    00C0: 00 00 01 00 00 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    00D0: 00 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    00E0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0100: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0110: 00 00 02 00 00 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0120: 00 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0130: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0150: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0160: 00 00 03 00 00 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0170: 00 00 00 00 04 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0180: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    01A0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    01B0: 00 00 00 00 01 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    01C0: 00 00 00 00 05 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    01D0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    01E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    01F0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0200: 00 00 01 00 01 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0210: 00 00 00 00 06 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0220: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0240: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0250: 00 00 02 00 01 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0260: 00 00 00 00 07 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0270: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0290: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    02A0: 00 00 03 00 01 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    02B0: 00 00 00 00 08 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    02C0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    02D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    02E0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    02F0: 00 00 00 00 02 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0300: 00 00 00 00 09 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0310: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0330: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0340: 00 00 01 00 02 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0350: 00 00 00 00 0A 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0360: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0380: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0390: 00 00 02 00 02 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    03A0: 00 00 00 00 0B 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    03B0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    03C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    03D0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    03E0: 00 00 03 00 02 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    03F0: 00 00 00 00 0C 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0400: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0410: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0420: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0430: 00 00 00 00 03 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0440: 00 00 00 00 0D 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    0450: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0460: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0470: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0480: 00 00 01 00 03 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    0490: 00 00 00 00 0E 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    04A0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    04B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    04C0: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    04D0: 00 00 02 00 03 00 00 00 00 00 00 00 0B 50 00 00&nb= sp; // .............P..
    04E0: 00 00 00 00 0F 00 00 00 01 00 00 00 00 00 00 00&nb= sp; // ................
    04F0: 17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0510: 00 00 00 00 19 00 00 00 00 00 00 00 00 00 00 00&nb= sp; // ................
    0520: 00 00 03 00 03 00 00 00 00 00 00 00 0C 18 00 00&nb= sp; // ................
    0530: 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 00&nb= sp; // .......0........
    0540: 03 00 00 00 0E 10 00 00 00 00 1C 30 00 00 00 00&nb= sp; // ...........0....
    0550: 00 00 00 01 0E 10 00 00 00 00 1C 30 00 04 00 00&nb= sp; // ...........0....
    0560: 00 00 00 01 0E 10 00 00 00 00 1C 30 00 08 00 00&nb= sp; // ...........0....
    0570: 00 00 00 01 0E 10 00 00 00 00 1C 30 00 0C 00 00&nb= sp; // ...........0....
    0580: 00 00 00 01 0F 14 00 00 00 00 00 00 00 00 04 30&nb= sp; // ...............0
    0590: 00 00 00 00 00 00 00 00 0F 14 00 00 01 00 00 00&nb= sp; // ................
    05A0: 00 00 08 30 00 00 00 00 00 00 00 00 0F 14 00 00&nb= sp; // ...0............
    05B0: 02 00 00 00 00 00 0C 30 00 00 00 00 00 00 00 00&nb= sp; // .......0........
    05C0: 0F 14 00 00 03 00 00 00 00 00 10 30 00 00 00 00&nb= sp; // ...........0....
    05D0: 00 00 00 00 0F 14 00 00 04 00 00 00 00 00 14 30&nb= sp; // ...............0
    05E0: 00 00 00 00 00 00 00 00 0F 14 00 00 05 00 00 00&nb= sp; // ................
    05F0: 00 00 18 30 00 00 00 00 00 00 00 00  &nb= sp;           // ...0....= ....

[/snip]

[/SAMI]

[Nishant]
I manually traversed through the code logic with the example given above an= d I think the logic can handle it.
Could you please point out the exact problem with the patch?
[/Nishant]

Please point me to the documentation or code that has a standardised way of= updating the ACPI table.

[SAMI] There is a reference implementation at https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/VExpre= ssPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c#L= 475-L487

[Nishant]
This expects the GIC structure to be present linearly in the memory.
The algorithm implemented in the code is flexible. It checks the ID of each= node present in the table and processes it only if it is of type EFI_= ACPI_6_4_GIC(0xB).
[/Nishant]

Regarding the use of the Dynamic Table Framework, there are no short-term p= lans to migrate to it.
For the use of dynamic table 
[/Nishant]

+      GicStructure =3D (EFI_ACPI_6_4_GIC_=
STRUCTURE *)StructureListHead;
 
+      // Disable the CPU if its MPID is p=
resent in the list.
 
+      MpidPresent =3D CheckIfMpidIsPresen=
t(
 
+        HobData->IsolatedCpu=
List.Mpid,
 
+        HobData->IsolatedCpu=
List.Count,
 
+        GicStructure->MPIDR<=
/pre>

 


+        );


 


+      if (MpidPresent =3D=3D TRUE) {

 


+        DEBUG ((


 


+          DEBUG_INFO,=



 


+          "Disab=
ling Core: %lu, MPID: 0x%llx in MADT\n",


 


+          GicStructur=
e->AcpiProcessorUid,


 


+          GicStructur=
e->MPIDR


 


+          ));


 


+        GicStructure->Flags =
=3D 0;


 


+      }


 


+    }


 


+


 


+    // Second element in the structure component he=
ader is length


 


+    StructureListHead +=3D StructureListHead[1];

 


+  }


 


+}


 


+


 


+/**


 


+  Callback to validate and/or update ACPI table.


 


+


 


+  On finding a MADT table, disable the isolated CPUs in the M=
ADT table. The


 


+  list of isolated CPUs are obtained from the HOB data.


 


+


 


+  @param[in] AcpiHeader  Target ACPI table.


 


+


 


+  @retval  TURE   Table validated/updated succ=
essfully.


 


+  @retval  FALSE  Error in Table validation/updatio=
n.


 


+**/


 


+STATIC


 


+BOOLEAN


 


+CheckAndUpdateAcpiTable (


 


+  IN EFI_ACPI_DESCRIPTION_HEADER  *AcpiHeader


 


+  )


 


+{


 


+  VOID *SystemIdHob;


 


+  SGI_PLATFORM_DESCRIPTOR *HobData;


 


+


 


+  // This check updates the MADT table to disable isolated CP=
Us present on the


 


+  // platform.


 


+  if (AcpiHeader->Signature =3D=3D EFI_ACPI_1_0_APIC_SIGNA=
TURE) {

[SAMI] Why EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTIO= N_TABLE_SIGNATURE is not used here?

[Nishant] I will update in the next version.

+    SystemIdHob =3D GetFirstGuidHob (&gArmSgiPl=
atformIdDescriptorGuid);
 
+    if (SystemIdHob !=3D NULL) {
 
+      HobData =3D (SGI_PLATFORM_DESCRIPTO=
R *)GET_GUID_HOB_DATA (SystemIdHob);
 
+      UpdateMadtTable (AcpiHeader, HobDat=
a);
 
+    }
 
+  }
 
+
 
+  return TRUE;
 
+}
 
+
 
 EFI_STATUS
 
 EFIAPI
 
 ArmSgiPkgEntryPoint (
 
@@ -25,7 +149,10 @@ ArmSgiPkgEntryPoint (
 {
 
   EFI_STATUS       &n=
bsp;      Status;
 
 
 
-  Status =3D LocateAndInstallAcpiFromFv (&gArmSgiAcpiTabl=
esGuid);
 
+  Status =3D LocateAndInstallAcpiFromFvConditional (
 
+           =
  &gArmSgiAcpiTablesGuid,
 
+           =
  &CheckAndUpdateAcpiTable
 
+           =
  );
 
   if (EFI_ERROR (Status)) {
 
     DEBUG ((DEBUG_ERROR, "%a: Failed to i=
nstall ACPI tables\n", __FUNCTION__));
 
     return Status;
 
diff --git a/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatform=
Peim.c b/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c
index 7df52cc4fd7c..f778dc8ac7c1 100644
--- a/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c<=
/pre>

+++ b/Platform/ARM/SgiPkg/Library/SgiPlatformPei/SgiPlatformPeim.c<=
/pre>

@@ -1,6 +1,6 @@


 /** @file


 


 *


 


-*  Copyright (c) 2018, ARM Limited. All rights reserved.

 


+*  Copyright (c) 2018-2022, ARM Limited. All rights reserved.=



 


 *


 


 *  SPDX-License-Identifier: BSD-2-Clause-Patent


 


 *


 


@@ -38,6 +38,8 @@ GetSgiSystemId (


   CONST VOID       &n=
bsp;            *NtF=
wCfgDtBlob;


 


   SGI_NT_FW_CONFIG_INFO_PPI     *NtF=
wConfigInfoPpi;


 


   EFI_STATUS       &n=
bsp;            Stat=
us;


 


+  UINT64         =
;            &n=
bsp;  IsolatedCpuCount;


 


+  UINT64         =
;             &=
nbsp; CoreCount;


 


 


 


   Status =3D PeiServicesLocatePpi (&gNtFwConfigDtInf=
oPpiGuid, 0, NULL,


 


           &=
nbsp;  (VOID**)&NtFwConfigInfoPpi);


 


@@ -83,6 +85,32 @@ GetSgiSystemId (


     HobData->MultiChipMode =3D fdt32_to_cpu=
 (*Property);


 


   }


 


 


 


+  Property =3D fdt_getprop (NtFwCfgDtBlob, Offset, "isol=
ated-cpu-list", NULL);


 


+  if (Property =3D=3D NULL) {


 


+    DEBUG ((DEBUG_INFO, "%s property not found=
\n", "isolated-cpu-list"));


 


+    HobData->IsolatedCpuList.Count =3D 0;


 


+  } else {


 


+    CopyMem (&IsolatedCpuCount, Property, sizeo=
f (IsolatedCpuCount));


 


+    CoreCount =3D


 


+      FixedPcdGet32 (PcdChipCount) *

 


+      FixedPcdGet32 (PcdClusterCount) *

 


+      FixedPcdGet32 (PcdCoreCount);


 


+    if (IsolatedCpuCount > CoreCount) {


 


+      DEBUG ((


 


+           =
 DEBUG_ERROR,


 


+           =
 "IsolatedCpuCount(%u) is higher than CoreCount(%u)\n",


 


+           =
 IsolatedCpuCount,


 


+           =
 CoreCount


 


+           =
 ));


 


+      return EFI_SUCCESS;

[SAMI] Is the status code returned here correct? Should this be EFI_INVALID= _PARAMETER? Also the function name GetSgiSystemId() seems to no longer refl= ect what the function does. Hace you considered renaming it.

[Nishant]
This is done intentionally, we want to keep booting even if the config prov= ided is corrupted.

I will update the function name in the next version.
[/Nishant]

+    }
 
+    CopyMem (
 
+      &HobData->IsolatedCpuList,

 


+      Property,


 


+      sizeof(HobData->IsolatedCpuList)=
 + (CoreCount * sizeof(UINT64))

[SAMI] Coding convention is not followed here and at other places. Can you = fix, please?

[Nishant] Will update in the next patch version.

+      );
 
+  }
 
+
 
   return EFI_SUCCESS;
 
 }
 
 
 
@@ -104,11 +132,24 @@ SgiPlatformPeim (
 {
 
   SGI_PLATFORM_DESCRIPTOR     &=
nbsp; *HobData;
 
   EFI_STATUS       &n=
bsp;            Stat=
us;
 
+  UINT64         =
;            &n=
bsp;  CoreCount;
 
+  UINTN         =
            &nb=
sp;   HobSize;
 
 
 
+  CoreCount =3D
 
+    FixedPcdGet32 (PcdChipCount) *
 
+    FixedPcdGet32 (PcdClusterCount) *
 
+    FixedPcdGet32 (PcdCoreCount);
 
+
 
+  // Additional size for SGI_ISOLATED_CPU_LIST.
 
+  // Size =3D (MPID register size in bytes * CoreCount) +

 


+  //        sizeof(SGI_PLA=
TFORM_DESCRIPTOR)


 


+  HobSize =3D


 


+    sizeof (SGI_PLATFORM_DESCRIPTOR) +


 


+    (CoreCount * sizeof(UINT64));


 


   // Create platform descriptor HOB


 


   HobData =3D (SGI_PLATFORM_DESCRIPTOR *)BuildGuidHob (<=
/pre>

 


           &=
nbsp;           &nbs=
p;            &=
nbsp;     &gArmSgiPlatformIdDescriptorGuid,


 


-           =
            &nb=
sp;            =
     sizeof (SGI_PLATFORM_DESCRIPTOR));


 


+           =
            &nb=
sp;            =
     HobSize);


 


 


 


   // Get the system id from the platform specific nt_fw_=
config device tree


 


   if (HobData =3D=3D NULL) {


 

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