From: "Cohen, Eugene" <eugene@hp.com>
To: Marvin H?user <Marvin.Haeuser@outlook.com>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "star.zeng@intel.com" <star.zeng@intel.com>
Subject: Re: Inquiry regarding early DxeIplPeim loading.
Date: Thu, 19 Jul 2018 15:40:00 +0000 [thread overview]
Message-ID: <AT5PR8401MB0340C886BC49F3775A9B30DAB4520@AT5PR8401MB0340.NAMPRD84.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <VI1PR0801MB179051467F88C6927328159D80520@VI1PR0801MB1790.eurprd08.prod.outlook.com>
Marvin,
> Though to be honest, I am not sure why these PPIs are exposed by
> DxeIplPeim instead of a dedicated module or maybe even PeiCore itself, if
> it's the de facto standard.
When we were originally facing the issue one of the ideas was in fact to move this to PeiCore. I don't recall why that path wasn't pursued.
> Also, if the change was done to avoid disabling CAR prematurely, why
> wasn't SEC code adapted?
This was an ARM SoC not X86 so the modules involved were different than what you're seeing. I'm trying to remember the specifics but it was long enough ago that it escapes me and my time machine is broken.
Eugene
prev parent reply other threads:[~2018-07-19 15:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-12 23:19 Inquiry regarding early DxeIplPeim loading Marvin H?user
2018-07-13 9:24 ` Zeng, Star
2018-07-13 13:25 ` Marvin H?user
2018-07-18 9:11 ` Zeng, Star
2018-07-18 21:36 ` Cohen, Eugene
2018-07-19 0:10 ` Marvin H?user
2018-07-19 15:40 ` Cohen, Eugene [this message]
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