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From: "Cohen, Eugene" <eugene@hp.com>
To: Evan Lloyd <Evan.Lloyd@arm.com>,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>,
	Heyi Guo <heyi.guo@linaro.org>
Cc: Alexei Fedorov <Alexei.Fedorov@arm.com>,
	"edk2-devel@lists.01.org" <edk2-devel@ml01.01.org>,
	"Andrew Fish (afish@apple.com)" <afish@apple.com>,
	Leif Lindholm <leif.lindholm@linaro.org>
Subject: Re: [PATCH] ArmPkg: Fix double GIC EIOR write per interrupt
Date: Wed, 10 Aug 2016 21:06:36 +0000	[thread overview]
Message-ID: <AT5PR84MB0291DC42DBC9AF176693358FB41D0@AT5PR84MB0291.NAMPRD84.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <AM5PR0801MB17625A70B65D4FA0358955648B1D0@AM5PR0801MB1762.eurprd08.prod.outlook.com>

> My description was not very clear, and the point is academic if you are
> happy with the solution.

I think it's important that we're aligned on how the GIC works so thanks for humoring me.

> However:
> The GIC spec has a state machine diagram (Figure 4.3), where:
> Transition D, pending to active and pending
> This transition occurs on acknowledgement of the interrupt by the PE
> for level-sensitive SPIs, SGIs,
> and PPIs.
> Transition B1 or B2, remove pending state
> This transition occurs when the interrupt has been deasserted by the
> peripheral, if the interrupt is a
> level-sensitive interrupt, or when software has changed the pending
> state.
> Transition E1 or E2, remove active state
> This transition occurs when software deactivates an interrupt for SPIs,
> SGIs, and PPIs.
> 
> I suspect that because we EOI ("deactivate" for E1/E2) without
> "deasserting" the peripheral interrupt then the GIC may restore the
> pending state (transition E2 instead of B2 then E1), which will look
> remarkably like a latch.

But no latching will occur because, for a level sensitive interrupt, the EOI-before deassert should manifest as transition E2 (caused by EOI) followed by transition B1 (caused by clearing the source).  This is per the text that transition B1 occurs if "the level-sensitive interrupt is pending only because of the assertion of an input signal, and that signal is deasserted".  So the transition is Active+Pending -> Pending -> Inactive for this odd ordering versus the more sensible Active+Pending -> Active -> Inactive.

> That looks like a pretty sensible way forward.  I'll vote for EFI_SUCCESS,
> white lies are sometimes needed.

Okay, what's the worst that can happen? :)

Perhaps the real test would be that a driver that uses HwInterrupt is shown to work equally well on a fake-EOI interface system as well as a real-EOI interface system.  I doubt if we have any common peripherals (timer block or serial port or whatever) to really test this.

Eugene



      reply	other threads:[~2016-08-10 21:06 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-05 16:59 [PATCH] ArmPkg: Fix double GIC EIOR write per interrupt evan.lloyd
2016-08-06  8:24 ` Ard Biesheuvel
2016-08-08 10:25   ` Alexei Fedorov
2016-08-08 10:32     ` Ard Biesheuvel
2016-08-08 10:40       ` Alexei Fedorov
2016-08-08 10:44         ` Ard Biesheuvel
2016-08-08 10:48           ` Alexei Fedorov
2016-08-08 10:49             ` Ard Biesheuvel
2016-08-08 10:56               ` Alexei Fedorov
2016-08-08 10:58                 ` Ard Biesheuvel
2016-08-08 11:06                   ` Alexei Fedorov
2016-08-08 11:08                     ` Ard Biesheuvel
2016-08-08 11:51                       ` Ard Biesheuvel
2016-08-08 13:22                         ` Cohen, Eugene
2016-08-08 13:42                           ` Ard Biesheuvel
2016-08-08 13:50                             ` Ard Biesheuvel
2016-08-10 17:38                               ` Evan Lloyd
2016-08-10 19:34                                 ` Cohen, Eugene
2016-08-10 20:31                                   ` Evan Lloyd
2016-08-10 21:06                                     ` Cohen, Eugene [this message]

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