From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-in21.apple.com (mail-out21.apple.com [17.171.2.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 175A01A1E2F for ; Sat, 22 Oct 2016 11:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; d=apple.com; s=mailout2048s; c=relaxed/simple; q=dns/txt; i=@apple.com; t=1477160386; h=From:Sender:Reply-To:Subject:Date:Message-id:To:Cc:MIME-version:Content-type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-reply-to:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=f9NMnl/jXycXNUsBTE8rwo/Z7rXgrXv3WPI+E3/8/Sk=; b=jyjNRnp2mHlzlcBFHpOoZZXBMZrshOaUIW84RN1HchIJ4U/x9b60dwJ8NN3ouRXI G0FPQUd7r7CbCXUJz53rfJFTiyUlLl7fYGbp47vKHyW220x5FEGE3TshqVZujB7l 060Mtyp72acrX80ylqsfBNYoZvl6ocdcVDW+RKsYUlf699fH55xiGLF/wjpV4cQQ gw97qjh6r87H0a9/kigXTEpNc0PIzx36MFvLtEfH+f4i0lx3Nmk9YDwaZNxlSSaQ 5Ij7l90FjksY490QTD+mk8cWUxntfpIpVLd51v4JVHTRZKJbniD3/c4Qi5QZ8hnX fOI2txPUimslTPVPDpOhuw==; Received: from relay25.apple.com (relay25.apple.com [17.171.128.106]) by mail-in21.apple.com (Apple Secure Mail Relay) with SMTP id 11.DD.04982.1CDAB085; Sat, 22 Oct 2016 14:19:46 -0400 (EDT) X-AuditID: 11ab0215-521ff70000001376-65-580badc11bd2 Received: from ma1-mmpp-sz10.apple.com (ma1-mmpp-sz10.apple.com [17.171.128.150]) by relay25.apple.com (Apple SCV relay) with SMTP id C3.40.24919.1CDAB085; Sat, 22 Oct 2016 14:19:45 -0400 (EDT) MIME-version: 1.0 Received: from [17.168.156.82] by ma1-mmpp-sz10.apple.com (Oracle Communications Messaging Server 8.0.1.1.0 64bit (built Jun 15 2016)) with ESMTPSA id <0OFG001S6O8UCF40@ma1-mmpp-sz10.apple.com>; Sat, 22 Oct 2016 11:19:45 -0700 (PDT) Sender: afish@apple.com From: Andrew Fish Message-id: Date: Sat, 22 Oct 2016 11:19:42 -0700 In-reply-to: Cc: "edk2-devel@lists.01.org" To: Rafael Machado References: X-Mailer: Apple Mail (2.3226) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMLMWRmVeSWpSXmKPExsUiuLohS/fQWu4Ig8X3jC32HDrKbLHz5Qx2 ByaPnbPusnt0z/7HEsAUxWWTkpqTWZZapG+XwJWxa8MJloKjvUwVF7u+sjQwLn/J2MXIySEh YCJx7M55ti5GLg4hgYOMEi/37meGSRye+JYRInGYUeLi3W8sIAleAUGJH5PvgdnMAmES8y+/ hOp+B9S9qYUNJCEsIC7x7swmsElsAsoSK+Z/YO9i5ABqtpHYusYEokRDYsLM3ywgYRYBVYnH 21NATE6BZIlzM9IhpptLzLjwhQnEFhEwk9g7awI7iC0ksJJRYslLBZByCQFZidm/vEAOkBDY wCZxYs8x9gmMQrOQHDoLyaEQtpbE90etQHEOIFte4uB5WYiwpsSze5/YIWxtiSfvLrAuYGRb xSicm5iZo5uZZ2Sol1hQkJOql5yfu4kRHAtMojsY578yPMQowMGoxMNbsIQ7Qog1say4MvcQ ozQHi5I4r8tKtgghgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjObnw42XnVrw2Ujz6RSf7R8u TV64Uayv6NRmkY4VCZdmJLA2TPc+9eNd+Zf3CQ4hlqEc+s4rLVfyHdSZJPlhufLsXesdt90y SJ14fYZ/sonOy6f9syI+Khm3rFix8UH7q8NSJWceLM1I82y0/RvTIqgSFipro8es2205g9Wa q3FHdKtoeHz0dCWW4oxEQy3mouJEABFCZ09mAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrELMWRmVeSWpSXmKPExsUiuLphmu7BtdwRBq+vGVnsOXSU2WLnyxns DkweO2fdZffonv2PJYApissmJTUnsyy1SN8ugStj14YTLAVHe5kqLnZ9ZWlgXP6SsYuRk0NC wETi8MS3ULaYxIV769m6GLk4hAQOM0pcvPuNBSTBKyAo8WPyPTCbWSBMYv7ll1BF7xglXm5q YQNJCAuIS7w7s4kZxGYTUJZYMf8DexcjB1CzjcTWNSYQJRoSE2b+ZgEJswioSjzengJicgok S5ybkQ4x3VxixoUvTCC2iICZxN5ZE9hBbCGBlYwSS14qgJRLCMhKzP7lNYFRYBaS22YhuQ3C 1pL4/qgVKM4BZMtLHDwvCxHWlHh27xM7hK0t8eTdBdYFjGyrGAWLUnMSK41M9RILCnJS9ZLz czcxQkI6awfj7ZtmhxgFOBiVeHhzl3BHCLEmlhVX5h5ilOBgVhLhnbKBPUKINyWxsiq1KD++ qDQntfgQozQHi5I4r1ohV4SQQHpiSWp2ampBahFMlomDU6qBsfXz521WrwNmL+FYmf5Ten9r g/Yk/b/bjK9uPLQ0fWLg9oB5WtmnF+WXTE6Y38UyXZDP594Rcb+K05vkJQs3x86cnfd0A9cW d52pax77372i5f1lQXj/6pIjHtZ6As+WuK/4ckN88VXtLdWevkLVolePJYUXbea9ESbWlbtQ 8naOJsur95PtPyuxFGckGmoxFxUnAgDuXAS7ZQIAAA== X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: Sec and Reset vector X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 22 Oct 2016 18:19:48 -0000 Content-Type: text/plain; CHARSET=US-ASCII Content-Transfer-Encoding: 7BIT > On Oct 22, 2016, at 10:03 AM, Marvin H?user wrote: > > Hey Rafael, > > There actually is some generic SEC code in UefiCpuPkg you might want to take a look at. It's generic because it does not have "Intel NDA" code, such as CAR (Cache-As-RAM) etc. > The Reset Vector may or may not be part of SecCore. It's either embedded within the SecCore module, or a separate file in the FFS. You can check the start/end address of the modules (e.g. with UEFITool) and find the Reset Vector file that way. > Rafael, There is some strange construction things going on with the SEC for X86. If you look in the FDF file you will see that the SEC is a PE/COFF (or TE) image and a raw binary for the 16-bit real mode reset vector code. https://github.com/tianocore/edk2/blob/master/Vlv2TbltDevicePkg/PlatformPkg.fdf#L876 [Rule.Common.SEC] FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { PE32 PE32 Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi RAW BIN Align = 16 |.com } The .com files are constructed from *.nasmb, *.asm16, or *.S16 files. https://github.com/tianocore/edk2/tree/master/UefiCpuPkg/SecCore/Ia32 Special extensions are needed to have special build rules. The build rules are here: https://github.com/tianocore/edk2/blob/master/BaseTools/Conf/build_rule.template#L480 Look at the [Masm16-Code-File] and [Nasm-to-Binary-Code-File] rules. The build tools also do some magic to stitch the .com and PE/COFF (TE) file together. https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/SecCore/Ia32/ResetVec.nasmb#L46 ; ; Pointer to the entry point of the PEI core ; It is located at 0xFFFFFFE0, and is fixed up by some build tool ; So if the value 8..1 appears in the final FD image, tool failure occurs. ; PeiCoreEntryPoint: DD 87654321h The reason you need special build rules is it is really hard to get code at the end of a PE/COFF file, so you need a stripped binary for the reset vector. The next problem is how do you get the FV File to be at the end of the FV (that is usually free space). The PI spec defines that if an FFS file has the File GUID of gEfiFirmwareVolumeTopFileGuid then it gets place at the end of the FV. Thus the X86 SEC must have this file guid. This also triggers the magic behavior to stitch the .com and PE/COFF together. https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/SecCore/SecCore.inf#L25 FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 For ARM things are much simpler. The FV reserves 16-bytes at the start of the volume for the reset vector. If the build tools see an FV has an ARM SEC it can patch in a branch to the SEC PE/COFF (TE) entry point (going from memory hopefully I did not botch that). https://github.com/tianocore/edk2/blob/master/MdePkg/Include/Pi/PiFirmwareVolume.h#L110 /// /// The first 16 bytes are reserved to allow for the reset vector of /// processors whose reset vector is at address 0. /// UINT8 ZeroVector[16]; > PS.: Seems like inline images are not supported by the mailing list (or is it my error?). Either way, I do not see the image in my mail client (Outlook 2016). > I don't see the image in my macOS Mail client. Thanks, Andrew Fish > Regards, > Marvin. > >> -----Original Message----- >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of >> Rafael Machado >> Sent: Saturday, October 22, 2016 6:28 PM >> To: edk2-devel@lists.01.org >> Subject: [edk2] Sec and Reset vector >> >> Hi eveyrone >> >> I'm doing some studies on edk2 and coreboot, but I'm having some questions >> that I believe you can help. >> >> On the journey to try to understand things since the beginning, so they make >> sense in future, I'm trying to understand how does the Initial phases of UEFI >> / PI firmware work. To do that I got a bios image and start to reverse it to >> check the modules and everything present at that bios. Now I understand, at >> least the basics, about DXE and PEI phase. >> >> The main question that I have now is about the SEC phase. >> To try to understand the SEC phase I tried to reverse this firmware so I could >> check the reset vector's first jump or something like that. >> The surprise I have is that I was not able to find this code. >> >> To be sure I was reversing on the correct way I generated a coreboot image. >> On the image below we can see the initial code of a firmware generated >> using coreboot >> >> [image: pasted1] >> >> But at the UEFI firmware I'm studying I'm not able to find anything similar to >> that. >> My guess before starting this was that at least the SEC initial code should be >> similar to the legacy way of doing things, a jmp at 0xfff:fff0 and after that the >> magic should get started with all uefi phases. >> >> Could someone please give me some light on that? >> >> >> Thanks and Regards >> Rafael R. Machado >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel