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From: "Wu, Hao A" <hao.a.wu@intel.com>
To: "Ni, Ruiyu" <ruiyu.ni@intel.com>,
	"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "Tian, Feng" <feng.tian@intel.com>, "Zeng, Star" <star.zeng@intel.com>
Subject: Re: [PATCH 2/3] MdeModulePkg/XhciDxe: Dump the CMD/EVENT/INT/BULK ring information
Date: Thu, 29 Jun 2017 08:44:54 +0000	[thread overview]
Message-ID: <B80AF82E9BFB8E4FBD8C89DA810C6A0931CC6E5C@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <20170628103959.397244-3-ruiyu.ni@intel.com>

Reviewed-by: Hao Wu <hao.a.wu@intel.com>


Best Regards,
Hao Wu


> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ruiyu
> Ni
> Sent: Wednesday, June 28, 2017 6:40 PM
> To: edk2-devel@lists.01.org
> Cc: Wu, Hao A; Tian, Feng; Zeng, Star
> Subject: [edk2] [PATCH 2/3] MdeModulePkg/XhciDxe: Dump the
> CMD/EVENT/INT/BULK ring information
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Feng Tian <feng.tian@intel.com>
> ---
>  MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 27
> ++++++++++++++++++++++++---
>  1 file changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
> b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
> index 93803c352e..dbc91023e1 100644
> --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
> +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
> @@ -604,8 +604,6 @@ XhcInitSched (
>    XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
>    XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT
> (CmdRingPhy));
> 
> -  DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc-
> >CmdRing.RingSeg0));
> -
>    //
>    // Disable the 'interrupter enable' bit in USB_CMD
>    // and clear IE & IP bit in all Interrupter X Management Registers.
> @@ -620,7 +618,10 @@ XhcInitSched (
>    // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
>    //
>    CreateEventRing (Xhc, &Xhc->EventRing);
> -  DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc-
> >EventRing.EventRingSeg0));
> +  DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT
> ring [%p~%p)\n",
> +    Xhc->CmdRing.RingSeg0,        (UINTN)Xhc->CmdRing.RingSeg0 + sizeof
> (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
> +    Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 +
> sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
> +    ));
>  }
> 
>  /**
> @@ -2671,6 +2672,11 @@ XhcInitializeEndpointContext (
>            EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
>            Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)
> EndpointTransferRing;
>            CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING
> *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
> +          DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",
> +                  EpDesc->EndpointAddress,
> +                  EndpointTransferRing->RingSeg0,
> +                  (UINTN) EndpointTransferRing->RingSeg0 +
> TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
> +                  ));
>          }
> 
>          break;
> @@ -2739,6 +2745,11 @@ XhcInitializeEndpointContext (
>            EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
>            Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)
> EndpointTransferRing;
>            CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING
> *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
> +          DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",
> +                  EpDesc->EndpointAddress,
> +                  EndpointTransferRing->RingSeg0,
> +                  (UINTN) EndpointTransferRing->RingSeg0 +
> TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
> +                  ));
>          }
>          break;
> 
> @@ -2853,6 +2864,11 @@ XhcInitializeEndpointContext64 (
>            EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
>            Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)
> EndpointTransferRing;
>            CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING
> *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
> +          DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
> +                  EpDesc->EndpointAddress,
> +                  EndpointTransferRing->RingSeg0,
> +                  (UINTN) EndpointTransferRing->RingSeg0 +
> TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
> +                  ));
>          }
> 
>          break;
> @@ -2921,6 +2937,11 @@ XhcInitializeEndpointContext64 (
>            EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
>            Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)
> EndpointTransferRing;
>            CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING
> *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
> +          DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",
> +                  EpDesc->EndpointAddress,
> +                  EndpointTransferRing->RingSeg0,
> +                  (UINTN) EndpointTransferRing->RingSeg0 +
> TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
> +                  ));
>          }
>          break;
> 
> --
> 2.12.2.windows.2
> 
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel


  reply	other threads:[~2017-06-29  8:43 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-28 10:39 [PATCH 0/3] Check timeout URB again after stopping endpoint Ruiyu Ni
2017-06-28 10:39 ` [PATCH 1/3] MdeModulePkg/XhciDxe: Refine IsTransferRingTrb and IsAsyncIntTrb Ruiyu Ni
2017-06-29  8:44   ` Wu, Hao A
2017-06-28 10:39 ` [PATCH 2/3] MdeModulePkg/XhciDxe: Dump the CMD/EVENT/INT/BULK ring information Ruiyu Ni
2017-06-29  8:44   ` Wu, Hao A [this message]
2017-06-28 10:39 ` [PATCH 3/3] MdeModulePkg/XhciDxe: Check timeout URB again after stopping endpoint Ruiyu Ni
2017-06-29 11:14   ` Wu, Hao A
2017-06-28 13:30 ` [PATCH 0/3] " Zeng, Star
2017-06-29  2:50   ` Ni, Ruiyu
2017-06-29  3:07     ` Zeng, Star

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