From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 812A221DF37A5 for ; Tue, 1 Aug 2017 21:38:06 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2017 21:40:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,309,1498546800"; d="scan'208";a="118472871" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga002.jf.intel.com with ESMTP; 01 Aug 2017 21:40:16 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 1 Aug 2017 21:40:15 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 1 Aug 2017 21:40:15 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.151]) by shsmsx102.ccr.corp.intel.com ([169.254.2.146]) with mapi id 14.03.0319.002; Wed, 2 Aug 2017 12:40:11 +0800 From: "Wu, Hao A" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Gao, Liming" , "Fan, Jeff" Thread-Topic: [PATCH] UefiCpuPkg SecCore: Fix operands of different size in bitwise operation Thread-Index: AQHTCzR7PE2Ed7sm1EGrbpjF+47+l6Jwe2hw Date: Wed, 2 Aug 2017 04:40:11 +0000 Message-ID: References: <1501639799-46452-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1501639799-46452-1-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg SecCore: Fix operands of different size in bitwise operation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Aug 2017 04:38:06 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Hao Wu Best Regards, Hao Wu > -----Original Message----- > From: Zeng, Star > Sent: Wednesday, August 02, 2017 10:10 AM > To: edk2-devel@lists.01.org > Cc: Zeng, Star; Wu, Hao A; Gao, Liming; Fan, Jeff > Subject: [PATCH] UefiCpuPkg SecCore: Fix operands of different size in bi= twise > operation >=20 > It is introduced by 9e9ca2100f22be29f1a53129d741f4305ff34a71. >=20 > Cc: Hao Wu > Cc: Liming Gao > Cc: Jeff Fan > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Star Zeng > --- > UefiCpuPkg/SecCore/SecMain.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c > index e9e243ca0585..173bbfcfcba4 100644 > --- a/UefiCpuPkg/SecCore/SecMain.c > +++ b/UefiCpuPkg/SecCore/SecMain.c > @@ -281,7 +281,7 @@ SecStartupPhase2( > // will be built based on them in PEI phase. > // > SecCoreData->PeiTemporaryRamBase =3D (VOID *)(((UINTN)SecCoreData- > >PeiTemporaryRamBase + 7) & ~0x07); > - SecCoreData->PeiTemporaryRamSize &=3D ~0x07; > + SecCoreData->PeiTemporaryRamSize &=3D ~(UINTN)0x07; > } else { > // > // No addition PPI, PpiList directly point to the common PPI list. > -- > 2.7.0.windows.1