From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8F2FB20954B86 for ; Mon, 19 Mar 2018 18:18:13 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2018 18:24:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,333,1517904000"; d="scan'208";a="209644760" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga005.jf.intel.com with ESMTP; 19 Mar 2018 18:24:41 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 19 Mar 2018 18:24:41 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.226]) by shsmsx102.ccr.corp.intel.com ([169.254.2.80]) with mapi id 14.03.0319.002; Tue, 20 Mar 2018 09:24:39 +0800 From: "Wu, Hao A" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , "Zeng, Star" Thread-Topic: [edk2] [PATCH] SourceLevelDebugPkg DebugCommUsb3: Return error when debug cap is reset Thread-Index: AQHTv4A9lTWZ2QKx/kqtMGK4/mNCCaPYU3qQ Date: Tue, 20 Mar 2018 01:24:39 +0000 Message-ID: References: <1521463542-135668-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1521463542-135668-1-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] SourceLevelDebugPkg DebugCommUsb3: Return error when debug cap is reset X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Mar 2018 01:18:14 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Hao Wu Best Regards, Hao Wu > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of St= ar > Zeng > Sent: Monday, March 19, 2018 8:46 PM > To: edk2-devel@lists.01.org > Cc: Ni, Ruiyu; Wu, Hao A; Zeng, Star > Subject: [edk2] [PATCH] SourceLevelDebugPkg DebugCommUsb3: Return error > when debug cap is reset >=20 > When source level debug is enabled, but debug cable is not connected, > XhcResetHC() in XhciReg.c will reset the host controller, the debug > capability registers will be also reset. After the code in > InitializeUsbDebugHardware() sets DCE bit and LSE bit to "1" in DCCTRL, > there will be DMA on 0 (the value of some debug capability registers > for data transfer is 0) address buffer, fault info like below will > appear when IOMMU based on VTd is enabled. >=20 > VER_REG - 0x00000010 > CAP_REG - 0x00D2008C40660462 > ECAP_REG - 0x0000000000F050DA > GSTS_REG - 0xC0000000 > RTADDR_REG - 0x0000000086512000 > CCMD_REG - 0x2800000000000000 > FSTS_REG - 0x00000002 > FECTL_REG - 0xC0000000 > FEDATA_REG - 0x00000000 > FEADDR_REG - 0x00000000 > FEUADDR_REG - 0x00000000 > FRCD_REG[0] - 0xC0000006000000A0 0000000000000000 > Fault Info - 0x0000000000000000 > Source - B00 D14 F00 > Type - 1 (read) > Reason - 6 > IVA_REG - 0x0000000000000000 > IOTLB_REG - 0x1200000000000000 >=20 > This patch is to return error for the case. >=20 > Cc: Ruiyu Ni > Cc: Hao Wu > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > .../DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c | > 8 ++++++++ > 1 file changed, 8 insertions(+) >=20 > diff --git > a/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommun > icationLibUsb3Common.c > b/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommun > icationLibUsb3Common.c > index fb9ca84fc7bc..86ecc2f9dbc7 100644 > --- > a/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommun > icationLibUsb3Common.c > +++ > b/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommun > icationLibUsb3Common.c > @@ -673,11 +673,19 @@ InitializeUsbDebugHardware ( > UINTN Index; > UINT8 TotalUsb3Port; > EFI_PHYSICAL_ADDRESS XhciOpRegister; > + UINT32 Dcddi1; >=20 > XhciOpRegister =3D Handle->XhciOpRegister; > TotalUsb3Port =3D MmioRead32 (((UINTN) Handle->XhciMmioBase + > XHC_HCSPARAMS1_OFFSET)) >> 24; >=20 > if (Handle->Initialized =3D=3D USB3DBG_NOT_ENABLED) { > + Dcddi1 =3D XhcReadDebugReg (Handle,XHC_DC_DCDDI1); > + if (Dcddi1 !=3D (UINT32)((XHCI_DEBUG_DEVICE_VENDOR_ID << 16) | > XHCI_DEBUG_DEVICE_PROTOCOL)) { > + // > + // The debug capability has been reset by other code, return devic= e error. > + // > + return EFI_DEVICE_ERROR; > + } > // > // If XHCI supports debug capability, hardware resource has been all= ocated, > // but it has not been enabled, try to enable again. > -- > 2.7.0.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel