From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DD00221157414 for ; Wed, 13 Jun 2018 00:53:21 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2018 00:53:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,217,1526367600"; d="scan'208";a="49494646" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga006.jf.intel.com with ESMTP; 13 Jun 2018 00:53:20 -0700 Received: from fmsmsx123.amr.corp.intel.com (10.18.125.38) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Jun 2018 00:53:20 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx123.amr.corp.intel.com (10.18.125.38) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Jun 2018 00:53:20 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.87]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.82]) with mapi id 14.03.0319.002; Wed, 13 Jun 2018 15:53:18 +0800 From: "Wu, Hao A" To: "Chen, Chen A" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , "Kinney, Michael D" Thread-Topic: [PATCH 09/37] DuetPkg: Removing ipf which is no longer supported from edk2. Thread-Index: AQHUAsi/kBHvhpoAzEuIB8gWtLnfYKRd0Yuw Date: Wed, 13 Jun 2018 07:53:17 +0000 Message-ID: References: <20180613034343.10552-1-chen.a.chen@intel.com> In-Reply-To: <20180613034343.10552-1-chen.a.chen@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 09/37] DuetPkg: Removing ipf which is no longer supported from edk2. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jun 2018 07:53:22 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Hao Wu Best Regards, Hao Wu > -----Original Message----- > From: Chen, Chen A > Sent: Wednesday, June 13, 2018 11:44 AM > To: edk2-devel@lists.01.org > Cc: Chen, Chen A; Ni, Ruiyu; Wu, Hao A; Kinney, Michael D > Subject: [PATCH 09/37] DuetPkg: Removing ipf which is no longer supported > from edk2. >=20 > Removing rules for Ipf sources file: > * Remove the source file which path with "ipf" and also listed in > [Sources.IPF] section of INF file. > * Remove the source file which listed in [Components.IPF] section > of DSC file and not listed in any other [Components] section. > * Remove the embedded Ipf code for MDE_CPU_IPF. >=20 > Removing rules for Inf file: > * Remove IPF from VALID_ARCHITECTURES comments. > * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. > * Remove the INF which only listed in [Components.IPF] section in DSC. > * Remove statements from [BuildOptions] that provide IPF specific flags. > * Remove any IPF sepcific sections. >=20 > Removing rules for Dec file: > * Remove [Includes.IPF] section from Dec. >=20 > Removing rules for Dsc file: > * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. > * Remove any IPF specific sections. > * Remove statements from [BuildOptions] that provide IPF specific flags. >=20 > Cc: Ruiyu Ni > Cc: Hao Wu > Cc: Michael D Kinney > Signed-off-by: chenc2 > Contributed-under: TianoCore Contribution Agreement 1.1 > --- > DuetPkg/EfiLdr/PeLoader.c | 6 - > .../DxeCoreReportStatusCodeLibFromHob.inf | 2 +- > DuetPkg/PciRootBridgeNoEnumerationDxe/Ipf/PcatIo.c | 459 ---------------= ------ > .../PciRootBridgeNoEnumeration.inf | 3 - > DuetPkg/SataControllerDxe/SataControllerDxe.inf | 2 +- > 5 files changed, 2 insertions(+), 470 deletions(-) > delete mode 100644 DuetPkg/PciRootBridgeNoEnumerationDxe/Ipf/PcatIo.c >=20 > diff --git a/DuetPkg/EfiLdr/PeLoader.c b/DuetPkg/EfiLdr/PeLoader.c > index 7fafdfb14b..8f71b22531 100644 > --- a/DuetPkg/EfiLdr/PeLoader.c > +++ b/DuetPkg/EfiLdr/PeLoader.c > @@ -630,12 +630,6 @@ EfiLdrPeCoffCheckImageMachineType ( > } > #endif >=20 > -#ifdef MDE_CPU_IPF > - if (MachineType =3D=3D EFI_IMAGE_MACHINE_IA64) { > - Status =3D EFI_SUCCESS; > - } > -#endif > - > return Status; > } >=20 > diff --git > a/DuetPkg/Library/DxeCoreReportStatusCodeLibFromHob/DxeCoreReportStatu > sCodeLibFromHob.inf > b/DuetPkg/Library/DxeCoreReportStatusCodeLibFromHob/DxeCoreReportStatu > sCodeLibFromHob.inf > index 9b4649c7d5..14381b6f70 100644 > --- > a/DuetPkg/Library/DxeCoreReportStatusCodeLibFromHob/DxeCoreReportStatu > sCodeLibFromHob.inf > +++ > b/DuetPkg/Library/DxeCoreReportStatusCodeLibFromHob/DxeCoreReportStatu > sCodeLibFromHob.inf > @@ -29,7 +29,7 @@ > # > # The following information is for reference only and not required by th= e build > tools. > # > -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC > +# VALID_ARCHITECTURES =3D IA32 X64 EBC > # >=20 > [Sources] > diff --git a/DuetPkg/PciRootBridgeNoEnumerationDxe/Ipf/PcatIo.c > b/DuetPkg/PciRootBridgeNoEnumerationDxe/Ipf/PcatIo.c > deleted file mode 100644 > index 97857c2981..0000000000 > --- a/DuetPkg/PciRootBridgeNoEnumerationDxe/Ipf/PcatIo.c > +++ /dev/null > @@ -1,459 +0,0 @@ > -/*++ > - > -Copyright (c) 2005 - 2012, Intel Corporation. All rights reserved.
> -This program and the accompanying materials > -are licensed and made available under the terms and conditions of the BS= D > License > -which accompanies this distribution. The full text of the license may b= e found > at > -http://opensource.org/licenses/bsd-license.php > - > -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS > OR IMPLIED. > - > -Module Name: > - PcatPciRootBridgeIo.c > - > -Abstract: > - > - EFI PC AT PCI Root Bridge Io Protocol > - > -Revision History > - > ---*/ > - > -#include "PcatPciRootBridge.h" > -#include > -#include "SalProc.h" > - > -#include EFI_GUID_DEFINITION (SalSystemTable) > - > -// > -// Might be good to put this in an include file, but people may start > -// using it! They should always access the EFI abstraction that is > -// contained in this file. Just a little information hiding. > -// > -#define PORT_TO_MEM(_Port) ( ((_Port) & 0xffffffffffff0000) | (((_Port) = & > 0xfffc) << 10) | ((_Port) & 0x0fff) ) > - > -// > -// Macro's with casts make this much easier to use and read. > -// > -#define PORT_TO_MEM8(_Port) (*(UINT8 *)(PORT_TO_MEM(_Port))) > -#define PORT_TO_MEM16(_Port) (*(UINT16 *)(PORT_TO_MEM(_Port))) > -#define PORT_TO_MEM32(_Port) (*(UINT32 *)(PORT_TO_MEM(_Port))) > - > -#define EFI_PCI_ADDRESS_IA64(_seg, _bus,_dev,_func,_reg) \ > - ( (UINT64) ( (((UINTN)_seg) << 24) + (((UINTN)_bus) << 16) + (((UINT= N)_dev) > << 11) + (((UINTN)_func) << 8) + ((UINTN)_reg)) ) > - > -// > -// Local variables for performing SAL Proc calls > -// > -PLABEL mSalProcPlabel; > -CALL_SAL_PROC mGlobalSalProc; > - > -EFI_STATUS > -PcatRootBridgeIoIoRead ( > - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, > - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, > - IN UINT64 UserAddress, > - IN UINTN Count, > - IN OUT VOID *UserBuffer > - ) > -{ > - PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData; > - UINTN InStride; > - UINTN OutStride; > - UINTN AlignMask; > - UINTN Address; > - PTR Buffer; > - UINT16 Data16; > - UINT32 Data32; > - > - > - if ( UserBuffer =3D=3D NULL ) { > - return EFI_INVALID_PARAMETER; > - } > - > - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); > - > - Address =3D (UINTN) UserAddress; > - Buffer.buf =3D (UINT8 *)UserBuffer; > - > - if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit )= { > - return EFI_INVALID_PARAMETER; > - } > - > - if ((UINT32)Width >=3D EfiPciWidthMaximum) { > - return EFI_INVALID_PARAMETER; > - } > - > - if ((Width & 0x03) =3D=3D EfiPciWidthUint64) { > - return EFI_INVALID_PARAMETER; > - } > - > - AlignMask =3D (1 << (Width & 0x03)) - 1; > - if ( Address & AlignMask ) { > - return EFI_INVALID_PARAMETER; > - } > - > - InStride =3D 1 << (Width & 0x03); > - OutStride =3D InStride; > - if (Width >=3DEfiPciWidthFifoUint8 && Width <=3D EfiPciWidthFifoUint64= ) { > - InStride =3D 0; > - } > - if (Width >=3DEfiPciWidthFillUint8 && Width <=3D EfiPciWidthFillUint64= ) { > - OutStride =3D 0; > - } > - Width =3D Width & 0x03; > - > - Address +=3D PrivateData->PhysicalIoBase; > - > - // > - // Loop for each iteration and move the data > - // > - > - switch (Width) { > - case EfiPciWidthUint8: > - for (; Count > 0; Count--, Buffer.buf +=3D OutStride, Address +=3D I= nStride) { > - MEMORY_FENCE(); > - *Buffer.ui8 =3D PORT_TO_MEM8(Address); > - MEMORY_FENCE(); > - } > - break; > - > - case EfiPciWidthUint16: > - for (; Count > 0; Count--, Buffer.buf +=3D OutStride, Address +=3D I= nStride) { > - MEMORY_FENCE(); > - if (Buffer.ui & 0x1) { > - Data16 =3D PORT_TO_MEM16(Address); > - *Buffer.ui8 =3D (UINT8)(Data16 & 0xff); > - *(Buffer.ui8+1) =3D (UINT8)((Data16 >> 8) & 0xff); > - } else { > - *Buffer.ui16 =3D PORT_TO_MEM16(Address); > - } > - MEMORY_FENCE(); > - } > - break; > - > - case EfiPciWidthUint32: > - for (; Count > 0; Count--, Buffer.buf +=3D OutStride, Address +=3D I= nStride) { > - MEMORY_FENCE(); > - if (Buffer.ui & 0x3) { > - Data32 =3D PORT_TO_MEM32(Address); > - *Buffer.ui8 =3D (UINT8)(Data32 & 0xff); > - *(Buffer.ui8+1) =3D (UINT8)((Data32 >> 8) & 0xff); > - *(Buffer.ui8+2) =3D (UINT8)((Data32 >> 16) & 0xff); > - *(Buffer.ui8+3) =3D (UINT8)((Data32 >> 24) & 0xff); > - } else { > - *Buffer.ui32 =3D PORT_TO_MEM32(Address); > - } > - MEMORY_FENCE(); > - } > - break; > - } > - > - return EFI_SUCCESS; > -} > - > -EFI_STATUS > -PcatRootBridgeIoIoWrite ( > - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, > - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, > - IN UINT64 UserAddress, > - IN UINTN Count, > - IN OUT VOID *UserBuffer > - ) > -{ > - PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData; > - UINTN InStride; > - UINTN OutStride; > - UINTN AlignMask; > - UINTN Address; > - PTR Buffer; > - UINT16 Data16; > - UINT32 Data32; > - > - if ( UserBuffer =3D=3D NULL ) { > - return EFI_INVALID_PARAMETER; > - } > - > - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); > - > - Address =3D (UINTN) UserAddress; > - Buffer.buf =3D (UINT8 *)UserBuffer; > - > - if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit )= { > - return EFI_INVALID_PARAMETER; > - } > - > - if (Width < 0 || Width >=3D EfiPciWidthMaximum) { > - return EFI_INVALID_PARAMETER; > - } > - > - if ((Width & 0x03) =3D=3D EfiPciWidthUint64) { > - return EFI_INVALID_PARAMETER; > - } > - > - AlignMask =3D (1 << (Width & 0x03)) - 1; > - if ( Address & AlignMask ) { > - return EFI_INVALID_PARAMETER; > - } > - > - InStride =3D 1 << (Width & 0x03); > - OutStride =3D InStride; > - if (Width >=3DEfiPciWidthFifoUint8 && Width <=3D EfiPciWidthFifoUint64= ) { > - InStride =3D 0; > - } > - if (Width >=3DEfiPciWidthFillUint8 && Width <=3D EfiPciWidthFillUint64= ) { > - OutStride =3D 0; > - } > - Width =3D Width & 0x03; > - > - Address +=3D PrivateData->PhysicalIoBase; > - > - // > - // Loop for each iteration and move the data > - // > - > - switch (Width) { > - case EfiPciWidthUint8: > - for (; Count > 0; Count--, Buffer.buf +=3D OutStride, Address +=3D I= nStride) { > - MEMORY_FENCE(); > - PORT_TO_MEM8(Address) =3D *Buffer.ui8; > - MEMORY_FENCE(); > - } > - break; > - > - case EfiPciWidthUint16: > - for (; Count > 0; Count--, Buffer.buf +=3D OutStride, Address +=3D I= nStride) { > - MEMORY_FENCE(); > - if (Buffer.ui & 0x1) { > - Data16 =3D *Buffer.ui8; > - Data16 =3D Data16 | (*(Buffer.ui8+1) << 8); > - PORT_TO_MEM16(Address) =3D Data16; > - } else { > - PORT_TO_MEM16(Address) =3D *Buffer.ui16; > - } > - MEMORY_FENCE(); > - } > - break; > - case EfiPciWidthUint32: > - for (; Count > 0; Count--, Buffer.buf +=3D OutStride, Address +=3D I= nStride) { > - MEMORY_FENCE(); > - if (Buffer.ui & 0x3) { > - Data32 =3D *Buffer.ui8; > - Data32 =3D Data32 | (*(Buffer.ui8+1) << 8); > - Data32 =3D Data32 | (*(Buffer.ui8+2) << 16); > - Data32 =3D Data32 | (*(Buffer.ui8+3) << 24); > - PORT_TO_MEM32(Address) =3D Data32; > - } else { > - PORT_TO_MEM32(Address) =3D *Buffer.ui32; > - } > - MEMORY_FENCE(); > - } > - break; > - } > - > - return EFI_SUCCESS; > -} > - > -EFI_STATUS > -PcatRootBridgeIoGetIoPortMapping ( > - OUT EFI_PHYSICAL_ADDRESS *IoPortMapping, > - OUT EFI_PHYSICAL_ADDRESS *MemoryPortMapping > - ) > -/*++ > - > - Get the IO Port Map from the SAL System Table. > - > ---*/ > -{ > - SAL_SYSTEM_TABLE_ASCENDING_ORDER *SalSystemTable; > - SAL_ST_MEMORY_DESCRIPTOR_ENTRY *SalMemDesc; > - EFI_STATUS Status; > - > - // > - // On all Itanium architectures, bit 63 is the I/O bit for performming= Memory > Mapped I/O operations > - // > - *MemoryPortMapping =3D 0x8000000000000000; > - > - Status =3D EfiLibGetSystemConfigurationTable(&gEfiSalSystemTableGuid, > &SalSystemTable); > - if (EFI_ERROR(Status)) { > - return EFI_NOT_FOUND; > - } > - > - // > - // BugBug: Add code to test checksum on the Sal System Table > - // > - if (SalSystemTable->Entry0.Type !=3D 0) { > - return EFI_UNSUPPORTED; > - } > - > - mSalProcPlabel.ProcEntryPoint =3D SalSystemTable->Entry0.SalProcEntry; > - mSalProcPlabel.GP =3D SalSystemTable->Entry0.GlobalDataPoi= nter; > - mGlobalSalProc =3D > (CALL_SAL_PROC)&mSalProcPlabel.ProcEntryPoint; > - > - // > - // The SalSystemTable pointer includes the Type 0 entry. > - // The SalMemDesc is Type 1 so it comes next. > - // > - SalMemDesc =3D (SAL_ST_MEMORY_DESCRIPTOR_ENTRY *)(SalSystemTable + > 1); > - while (SalMemDesc->Type =3D=3D SAL_ST_MEMORY_DESCRIPTOR) { > - if (SalMemDesc->MemoryType =3D=3D SAL_IO_PORT_MAPPING) { > - *IoPortMapping =3D SalMemDesc->PhysicalMemoryAddress; > - *IoPortMapping |=3D 0x8000000000000000; > - return EFI_SUCCESS; > - } > - SalMemDesc++; > - } > - return EFI_UNSUPPORTED; > -} > - > -EFI_STATUS > -PcatRootBridgeIoPciRW ( > - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, > - IN BOOLEAN Write, > - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, > - IN UINT64 UserAddress, > - IN UINTN Count, > - IN OUT UINT8 *UserBuffer > - ) > -{ > - PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData; > - UINTN AlignMask; > - UINTN InStride; > - UINTN OutStride; > - UINT64 Address; > - DEFIO_PCI_ADDR *Defio; > - PTR Buffer; > - UINT32 Data32; > - UINT16 Data16; > - rArg Return; > - > - if (Width < 0 || Width >=3D EfiPciWidthMaximum) { > - return EFI_INVALID_PARAMETER; > - } > - > - if ((Width & 0x03) =3D=3D EfiPciWidthUint64) { > - return EFI_INVALID_PARAMETER; > - } > - > - AlignMask =3D (1 << (Width & 0x03)) - 1; > - if ( UserAddress & AlignMask ) { > - return EFI_INVALID_PARAMETER; > - } > - > - InStride =3D 1 << (Width & 0x03); > - OutStride =3D InStride; > - if (Width >=3DEfiPciWidthFifoUint8 && Width <=3D EfiPciWidthFifoUint64= ) { > - InStride =3D 0; > - } > - if (Width >=3DEfiPciWidthFillUint8 && Width <=3D EfiPciWidthFillUint64= ) { > - OutStride =3D 0; > - } > - Width =3D Width & 0x03; > - > - Defio =3D (DEFIO_PCI_ADDR *)&UserAddress; > - > - if ((Defio->Function > PCI_MAX_FUNC) || (Defio->Device > > PCI_MAX_DEVICE)) { > - return EFI_UNSUPPORTED; > - } > - > - Buffer.buf =3D (UINT8 *)UserBuffer; > - > - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); > - > - Address =3D EFI_PCI_ADDRESS_IA64( > - This->SegmentNumber, > - Defio->Bus, > - Defio->Device, > - Defio->Function, > - Defio->Register > - ); > - > - // > - // PCI Config access are all 32-bit alligned, but by accessing the > - // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle type= s > - // are possible on PCI. > - // > - // SalProc takes care of reading the proper register depending on stri= de > - // > - > - EfiAcquireLock(&PrivateData->PciLock); > - > - while (Count) { > - > - if(Write) { > - > - if (Buffer.ui & 0x3) { > - Data32 =3D (*(Buffer.ui8+0) << 0); > - Data32 |=3D (*(Buffer.ui8+1) << 8); > - Data32 |=3D (*(Buffer.ui8+2) << 16); > - Data32 |=3D (*(Buffer.ui8+3) << 24); > - } else { > - Data32 =3D *Buffer.ui32; > - } > - > - Return.p0 =3D -3; > - Return =3D mGlobalSalProc((UINT64) SAL_PCI_CONFIG_WRITE, > - Address, 1 << Width, Data32, 0, 0, 0, 0= ); > - > - if(Return.p0) { > - EfiReleaseLock(&PrivateData->PciLock); > - return EFI_UNSUPPORTED; > - } > - > - } else { > - > - Return.p0 =3D -3; > - Return =3D mGlobalSalProc((UINT64) SAL_PCI_CONFIG_READ, > - Address, 1 << Width, 0, 0, 0, 0, 0); > - > - if(Return.p0) { > - EfiReleaseLock(&PrivateData->PciLock); > - return EFI_UNSUPPORTED; > - } > - > - switch (Width) { > - case EfiPciWidthUint8: > - *Buffer.ui8 =3D (UINT8)Return.p1; > - break; > - case EfiPciWidthUint16: > - if (Buffer.ui & 0x1) { > - Data16 =3D (UINT16)Return.p1; > - *(Buffer.ui8 + 0) =3D Data16 & 0xff; > - *(Buffer.ui8 + 1) =3D (Data16 >> 8) & 0xff; > - } else { > - *Buffer.ui16 =3D (UINT16)Return.p1; > - } > - break; > - case EfiPciWidthUint32: > - if (Buffer.ui & 0x3) { > - Data32 =3D (UINT32)Return.p1; > - *(Buffer.ui8 + 0) =3D (UINT8)(Data32 & 0xff); > - *(Buffer.ui8 + 1) =3D (UINT8)((Data32 >> 8) & 0xff); > - *(Buffer.ui8 + 2) =3D (UINT8)((Data32 >> 16) & 0xff); > - *(Buffer.ui8 + 3) =3D (UINT8)((Data32 >> 24) & 0xff); > - } else { > - *Buffer.ui32 =3D (UINT32)Return.p1; > - } > - break; > - } > - } > - > - Address +=3D InStride; > - Buffer.buf +=3D OutStride; > - Count -=3D 1; > - } > - > - EfiReleaseLock(&PrivateData->PciLock); > - > - return EFI_SUCCESS; > -} > - > -EFI_STATUS > -ScanPciRootBridgeForRoms( > - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev > - ) > - > -{ > - return EFI_UNSUPPORTED; > -} > diff --git > a/DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf > b/DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf > index 8f7ef1b17d..b7d9c51546 100644 > --- > a/DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf > +++ > b/DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf > @@ -53,9 +53,6 @@ > [Sources.x64] > X64/PcatIo.c >=20 > -[Sources.ipf] > - Ipf/PcatIo.c > - > [Protocols] > gEfiPciRootBridgeIoProtocolGuid > gEfiDeviceIoProtocolGuid > diff --git a/DuetPkg/SataControllerDxe/SataControllerDxe.inf > b/DuetPkg/SataControllerDxe/SataControllerDxe.inf > index b3b37ddd0e..3608956f57 100644 > --- a/DuetPkg/SataControllerDxe/SataControllerDxe.inf > +++ b/DuetPkg/SataControllerDxe/SataControllerDxe.inf > @@ -24,7 +24,7 @@ > # > # The following information is for reference only and not required by th= e build > tools. > # > -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC > +# VALID_ARCHITECTURES =3D IA32 X64 EBC > # >=20 > [Sources] > -- > 2.16.2.windows.1