From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel-bounces@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 92823211211FC; Sun, 9 Sep 2018 18:22:17 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Sep 2018 18:22:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,354,1531810800"; d="scan'208,217";a="71888966" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga008.jf.intel.com with ESMTP; 09 Sep 2018 18:22:16 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 9 Sep 2018 18:22:16 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 9 Sep 2018 18:22:15 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.143]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.205]) with mapi id 14.03.0319.002; Mon, 10 Sep 2018 09:22:12 +0800 From: "Wu, Hao A" To: "Wang, Jian J" , edk2-devel , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH] UefiCpuPkg/CpuDxe: fix an incorrect bit-wise operation Thread-Index: AQHURx5kv4FR6elCIEanCys46VyyLqTlMpqAgAACKACAA4ZEUA== Date: Mon, 10 Sep 2018 01:22:12 +0000 Message-ID: References: <20180908024802.13488-1-jian.j.wang@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: Re: [PATCH] UefiCpuPkg/CpuDxe: fix an incorrect bit-wise operation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Sep 2018 01:22:17 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Hao Wu Best Regards, Hao Wu From: Wang, Jian J Sent: Saturday, September 08, 2018 11:32 AM To: edk2-devel; edk2-devel@lists.01.org Cc: Wu, Hao A Subject: RE: [edk2] [PATCH] UefiCpuPkg/CpuDxe: fix an incorrect bit-wise op= eration And BZ#1164: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1164 Regards, Jian From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] Sent: Saturday, September 08, 2018 11:25 AM To: edk2-devel ; edk2-devel@lists.01.org Cc: Wu, Hao A Subject: Re: [edk2] [PATCH] UefiCpuPkg/CpuDxe: fix an incorrect bit-wise op= eration Forgot to mention BZ info: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1095 Regards, Jian > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] > Sent: Saturday, September 08, 2018 10:48 AM > To: edk2-devel@lists.01.org > Cc: Wu, Hao A > > Subject: [edk2] [PATCH] UefiCpuPkg/CpuDxe: fix an incorrect bit-wise oper= ation > > The left operand is 64-bit but right operand could be 32-bit. > A typecast is a must because of '~' op before it. > > Cc: Hao A Wu > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jian J Wang > > --- > UefiCpuPkg/CpuDxe/CpuPageTable.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c > b/UefiCpuPkg/CpuDxe/CpuPageTable.c > index ef6e080a07..0a980b9753 100644 > --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c > +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c > @@ -1181,7 +1181,7 @@ DebugExceptionHandler ( > > for (PFEntry =3D 0; PFEntry < mPFEntryCount[CpuIndex]; PFEntry++) { > if (mLastPFEntryPointer[CpuIndex][PFEntry] !=3D NULL) { > - *mLastPFEntryPointer[CpuIndex][PFEntry] &=3D ~IA32_PG_P; > + *mLastPFEntryPointer[CpuIndex][PFEntry] &=3D ~(UINT64)IA32_PG_P; > } > } > > -- > 2.16.2.windows.1 > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel