From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D14F121129447 for ; Mon, 17 Sep 2018 00:18:08 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Sep 2018 00:18:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,384,1531810800"; d="scan'208";a="233512254" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga004.jf.intel.com with ESMTP; 17 Sep 2018 00:17:54 -0700 Received: from fmsmsx156.amr.corp.intel.com (10.18.116.74) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 17 Sep 2018 00:17:53 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx156.amr.corp.intel.com (10.18.116.74) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 17 Sep 2018 00:17:53 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.143]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.16]) with mapi id 14.03.0319.002; Mon, 17 Sep 2018 15:17:51 +0800 From: "Wu, Hao A" To: Marcin Wojtas , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" , "Gao, Liming" , "leif.lindholm@linaro.org" , "ard.biesheuvel@linaro.org" , "nadavh@marvell.com" , "jsd@semihalf.com" , "tm@semihalf.com" Thread-Topic: [PATCH v3 1/3] MdeModulePkg/SdMmcPciHcDxe: Adjust eMMC clock and bus width sequence Thread-Index: AQHUTUMbt0F2U7K0xUSIvFThu35b6KT0DnAA Date: Mon, 17 Sep 2018 07:17:51 +0000 Message-ID: References: <1537050346-16445-1-git-send-email-mw@semihalf.com> <1537050346-16445-2-git-send-email-mw@semihalf.com> In-Reply-To: <1537050346-16445-2-git-send-email-mw@semihalf.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 1/3] MdeModulePkg/SdMmcPciHcDxe: Adjust eMMC clock and bus width sequence X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Sep 2018 07:18:09 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Marcin Wojtas [mailto:mw@semihalf.com] > Sent: Sunday, September 16, 2018 6:26 AM > To: edk2-devel@lists.01.org > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org;= Wu, > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com; mw@semihalf.com; > jsd@semihalf.com; tm@semihalf.com > Subject: [PATCH v3 1/3] MdeModulePkg/SdMmcPciHcDxe: Adjust eMMC clock > and bus width sequence >=20 > According to JESD84-B50-1 chapter A.6 (documentation about eMMC4.5 > standard) step "Changing the data bus width" (A.6.3) should be > executed after step "Switching to high-speed mode" (A.6.2). Hi, My understanding to the spec is that the spec seems do not impose a sequence for 'Switching to high-speed mode' and 'Changing the data bus width'. My find is that both operation (A.6.2 & A.6.3 of JESD84-B50-1 ) requires: * Do these steps after the bus is initialized according to A.6.1, Bus * initialization. Also, for HS200 mode selection, the flow chart in Section 6.6.4 shows the bus width set before bus mode switch. So I think the current code is taking this as a reference when switching the 'High Speed' mode. I tried the eMMC device on my side, the current code implementation and codes after applying your patch both work. So do you met with issues with certain device with this sequence? If not, I prefer to keep the current logic. Best Regards, Hao Wu >=20 > This patch fixes the bus-width/clock-setting sequence > in EmmcSwitchToHighSpeed (). >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > index c5fd214..12935ef 100755 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > @@ -745,10 +745,6 @@ EmmcSwitchToHighSpeed ( > UINT8 HostCtrl1; > UINT8 HostCtrl2; >=20 > - Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusW= idth); > - if (EFI_ERROR (Status)) { > - return Status; > - } > // > // Set to Hight Speed timing > // > @@ -783,6 +779,11 @@ EmmcSwitchToHighSpeed ( >=20 > HsTiming =3D 1; > Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, > ClockFreq); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusW= idth); >=20 > return Status; > } > -- > 2.7.4