From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 674ED21129447 for ; Mon, 17 Sep 2018 00:17:57 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Sep 2018 00:17:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,384,1531810800"; d="scan'208";a="74875729" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga006.jf.intel.com with ESMTP; 17 Sep 2018 00:17:56 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 17 Sep 2018 00:17:56 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.143]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.205]) with mapi id 14.03.0319.002; Mon, 17 Sep 2018 15:17:55 +0800 From: "Wu, Hao A" To: Marcin Wojtas , "edk2-devel@lists.01.org" CC: "tm@semihalf.com" , "nadavh@marvell.com" , "Gao, Liming" , "Kinney, Michael D" Thread-Topic: [edk2] [PATCH v3 2/3] MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcHcReset to set only necesery bits Thread-Index: AQHUTUMh9ALk2UU6SUmpMyHacm26ZqT0EL6g Date: Mon, 17 Sep 2018 07:17:55 +0000 Message-ID: References: <1537050346-16445-1-git-send-email-mw@semihalf.com> <1537050346-16445-3-git-send-email-mw@semihalf.com> In-Reply-To: <1537050346-16445-3-git-send-email-mw@semihalf.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 2/3] MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcHcReset to set only necesery bits X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Sep 2018 07:17:58 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Marcin Wojtas > Sent: Sunday, September 16, 2018 6:26 AM > To: edk2-devel@lists.01.org > Cc: Tian, Feng; tm@semihalf.com; Wu, Hao A; nadavh@marvell.com; Gao, > Liming; Kinney, Michael D > Subject: [edk2] [PATCH v3 2/3] MdeModulePkg/SdMmcPciHcDxe: Fix > SdMmcHcReset to set only necesery bits >=20 > From: Tomasz Michalec >=20 > SdMmcHcReset used to set all bits of Software Reset Register to 1 > including reserved ones. Hi, I did a quick search of the SD Host Controller Simplified Specification, I do not find the spec prohibit setting all the bits when performing a reset for the host controller. Do you met with issues during the controller reset with the current logic? Best Regards, Hao Wu >=20 > Now only first bit is set which means "Software Reset for All". >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 5 +++++ > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 6 +++--- > 2 files changed, 8 insertions(+), 3 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > index e389d52..bcc31bd 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > @@ -63,6 +63,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY > KIND, EITHER EXPRESS OR IMPLIED. > #define SD_MMC_HC_CTRL_VER 0xFE >=20 > // > +// SD Software Reset Register bits description > +// > +#define SD_MMC_HC_SW_RST_ALL BIT0 > + > +// > // The transfer modes supported by SD Host Controller > // Simplified Spec 3.0 Table 1-2 > // > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index 9672b5b..9d9bca8 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -454,8 +454,8 @@ SdMmcHcReset ( > } >=20 > PciIo =3D Private->PciIo; > - SwReset =3D 0xFF; > - Status =3D SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_SW_RST, FALSE, sizeo= f > (SwReset), &SwReset); > + SwReset =3D SD_MMC_HC_SW_RST_ALL; > + Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof > (SwReset), &SwReset); >=20 > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write full 1 fails: %r\n", Statu= s)); > @@ -467,7 +467,7 @@ SdMmcHcReset ( > Slot, > SD_MMC_HC_SW_RST, > sizeof (SwReset), > - 0xFF, > + SD_MMC_HC_SW_RST_ALL, > 0x00, > SD_MMC_HC_GENERIC_TIMEOUT > ); > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel