* [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API
2018-09-20 6:40 [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Hao Wu
@ 2018-09-20 6:40 ` Hao Wu
2018-09-20 13:13 ` Laszlo Ersek
2018-09-20 6:41 ` [PATCH v1 2/5] MdeModulePkg/FaultTolerantWrite:[CVE-2017-5753]Fix bounds check bypass Hao Wu
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Hao Wu @ 2018-09-20 6:40 UTC (permalink / raw)
To: edk2-devel
Cc: Hao Wu, Ard Biesheuvel, Laszlo Ersek, Jiewen Yao,
Michael D Kinney, Liming Gao
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1193
This commit will add a new BaseLib API LoadFence(). This API will perform
a serializing operation on all load-from-memory instructions that were
issued prior to the call of this function.
The purpose of adding this API is to mitigate of the [CVE-2017-5753]
Bounds Check Bypass issue when untrusted data are being processed within
SMM. More details can be referred at the 'Bounds check bypass mitigation'
section at the below link:
https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
MdePkg/Include/Library/BaseLib.h | 12 +++++++
MdePkg/Library/BaseLib/Arm/LoadFence.c | 26 ++++++++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 4 +++
MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c | 15 +++++++-
MdePkg/Library/BaseLib/Ia32/LoadFence.nasm | 37 +++++++++++++++++++
MdePkg/Library/BaseLib/X64/LoadFence.nasm | 38 ++++++++++++++++++++
6 files changed, 131 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 123ae19dc2..194726ca35 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -4939,6 +4939,18 @@ MemoryFence (
/**
+ Performs a serializing operation on all load-from-memory instructions that
+ were issued prior to the call of this function.
+
+**/
+VOID
+EFIAPI
+LoadFence (
+ VOID
+ );
+
+
+/**
Saves the current CPU context that can be restored with a call to LongJump()
and returns 0.
diff --git a/MdePkg/Library/BaseLib/Arm/LoadFence.c b/MdePkg/Library/BaseLib/Arm/LoadFence.c
new file mode 100644
index 0000000000..69f0c3a07e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Arm/LoadFence.c
@@ -0,0 +1,26 @@
+/** @file
+ LoadFence() function for ARM.
+
+ Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+/**
+ Performs a serializing operation on all load-from-memory instructions that
+ were issued prior to the call of this function.
+
+**/
+VOID
+EFIAPI
+LoadFence (
+ VOID
+ )
+{
+}
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index a1b5ec4b75..f028fbc75a 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -68,6 +68,7 @@
[Sources.Ia32]
Ia32/WriteTr.nasm
+ Ia32/LoadFence.nasm
Ia32/Wbinvd.c | MSFT
Ia32/WriteMm7.c | MSFT
@@ -346,6 +347,7 @@
X64/EnableCache.nasm
X64/DisableCache.nasm
X64/WriteTr.nasm
+ X64/LoadFence.nasm
X64/CpuBreakpoint.c | MSFT
X64/WriteMsr64.c | MSFT
@@ -580,6 +582,7 @@
[Sources.ARM]
Arm/InternalSwitchStack.c
Arm/Unaligned.c
+ Arm/LoadFence.c
Math64.c | RVCT
Math64.c | MSFT
@@ -613,6 +616,7 @@
[Sources.AARCH64]
Arm/InternalSwitchStack.c
Arm/Unaligned.c
+ Arm/LoadFence.c
Math64.c
AArch64/MemoryFence.S | GCC
diff --git a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
index 9b7d875664..a79461cfbf 100644
--- a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
+++ b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
@@ -1,7 +1,7 @@
/** @file
Base Library CPU Functions for EBC
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -52,6 +52,19 @@ MemoryFence (
}
/**
+ Performs a serializing operation on all load-from-memory instructions that
+ were issued prior to the call of this function.
+
+**/
+VOID
+EFIAPI
+LoadFence (
+ VOID
+ )
+{
+}
+
+/**
Disables CPU interrupts.
**/
diff --git a/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
new file mode 100644
index 0000000000..11600bea76
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; LoadFence.nasm
+;
+; Abstract:
+;
+; Performs a serializing operation on all load-from-memory instructions that
+; were issued prior to the call of this function.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; LoadFence (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(LoadFence)
+ASM_PFX(LoadFence):
+ lfence
+ ret
+
diff --git a/MdePkg/Library/BaseLib/X64/LoadFence.nasm b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
new file mode 100644
index 0000000000..c076d9789d
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
@@ -0,0 +1,38 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; LoadFence.nasm
+;
+; Abstract:
+;
+; Performs a serializing operation on all load-from-memory instructions that
+; were issued prior to the call of this function.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; LoadFence (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(LoadFence)
+ASM_PFX(LoadFence):
+ lfence
+ ret
+
--
2.12.0.windows.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API
2018-09-20 6:40 ` [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API Hao Wu
@ 2018-09-20 13:13 ` Laszlo Ersek
2018-09-21 2:14 ` Wu, Hao A
2018-09-21 2:38 ` Wu, Hao A
0 siblings, 2 replies; 13+ messages in thread
From: Laszlo Ersek @ 2018-09-20 13:13 UTC (permalink / raw)
To: Hao Wu, edk2-devel
Cc: Ard Biesheuvel, Jiewen Yao, Michael D Kinney, Liming Gao,
Leif Lindholm (Linaro address)
On 09/20/18 08:40, Hao Wu wrote:
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1193
>
> This commit will add a new BaseLib API LoadFence(). This API will perform
> a serializing operation on all load-from-memory instructions that were
> issued prior to the call of this function.
>
> The purpose of adding this API is to mitigate of the [CVE-2017-5753]
> Bounds Check Bypass issue when untrusted data are being processed within
> SMM. More details can be referred at the 'Bounds check bypass mitigation'
> section at the below link:
>
> https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation
>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Hao Wu <hao.a.wu@intel.com>
> ---
> MdePkg/Include/Library/BaseLib.h | 12 +++++++
> MdePkg/Library/BaseLib/Arm/LoadFence.c | 26 ++++++++++++++
> MdePkg/Library/BaseLib/BaseLib.inf | 4 +++
> MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c | 15 +++++++-
> MdePkg/Library/BaseLib/Ia32/LoadFence.nasm | 37 +++++++++++++++++++
> MdePkg/Library/BaseLib/X64/LoadFence.nasm | 38 ++++++++++++++++++++
> 6 files changed, 131 insertions(+), 1 deletion(-)
>
> diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> index 123ae19dc2..194726ca35 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -4939,6 +4939,18 @@ MemoryFence (
>
>
> /**
> + Performs a serializing operation on all load-from-memory instructions that
> + were issued prior to the call of this function.
> +
> +**/
> +VOID
> +EFIAPI
> +LoadFence (
> + VOID
> + );
> +
> +
> +/**
> Saves the current CPU context that can be restored with a call to LongJump()
> and returns 0.
>
> diff --git a/MdePkg/Library/BaseLib/Arm/LoadFence.c b/MdePkg/Library/BaseLib/Arm/LoadFence.c
> new file mode 100644
> index 0000000000..69f0c3a07e
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/Arm/LoadFence.c
> @@ -0,0 +1,26 @@
> +/** @file
> + LoadFence() function for ARM.
> +
> + Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +**/
> +
> +/**
> + Performs a serializing operation on all load-from-memory instructions that
> + were issued prior to the call of this function.
> +
> +**/
> +VOID
> +EFIAPI
> +LoadFence (
> + VOID
> + )
> +{
> +}
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
> index a1b5ec4b75..f028fbc75a 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -68,6 +68,7 @@
>
> [Sources.Ia32]
> Ia32/WriteTr.nasm
> + Ia32/LoadFence.nasm
>
> Ia32/Wbinvd.c | MSFT
> Ia32/WriteMm7.c | MSFT
> @@ -346,6 +347,7 @@
> X64/EnableCache.nasm
> X64/DisableCache.nasm
> X64/WriteTr.nasm
> + X64/LoadFence.nasm
>
> X64/CpuBreakpoint.c | MSFT
> X64/WriteMsr64.c | MSFT
> @@ -580,6 +582,7 @@
> [Sources.ARM]
> Arm/InternalSwitchStack.c
> Arm/Unaligned.c
> + Arm/LoadFence.c
> Math64.c | RVCT
> Math64.c | MSFT
>
> @@ -613,6 +616,7 @@
> [Sources.AARCH64]
> Arm/InternalSwitchStack.c
> Arm/Unaligned.c
> + Arm/LoadFence.c
> Math64.c
>
> AArch64/MemoryFence.S | GCC
> diff --git a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> index 9b7d875664..a79461cfbf 100644
> --- a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> +++ b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> @@ -1,7 +1,7 @@
> /** @file
> Base Library CPU Functions for EBC
>
> - Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD License
> which accompanies this distribution. The full text of the license may be found at
> @@ -52,6 +52,19 @@ MemoryFence (
> }
>
> /**
> + Performs a serializing operation on all load-from-memory instructions that
> + were issued prior to the call of this function.
> +
> +**/
> +VOID
> +EFIAPI
> +LoadFence (
> + VOID
> + )
> +{
> +}
> +
> +/**
> Disables CPU interrupts.
>
> **/
> diff --git a/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> new file mode 100644
> index 0000000000..11600bea76
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> @@ -0,0 +1,37 @@
> +;------------------------------------------------------------------------------ ;
> +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +; This program and the accompanying materials
> +; are licensed and made available under the terms and conditions of the BSD License
> +; which accompanies this distribution. The full text of the license may be found at
> +; http://opensource.org/licenses/bsd-license.php.
> +;
> +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +;
> +; Module Name:
> +;
> +; LoadFence.nasm
> +;
> +; Abstract:
> +;
> +; Performs a serializing operation on all load-from-memory instructions that
> +; were issued prior to the call of this function.
> +;
> +; Notes:
> +;
> +;------------------------------------------------------------------------------
> +
> + SECTION .text
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EFIAPI
> +; LoadFence (
> +; VOID
> +; );
> +;------------------------------------------------------------------------------
> +global ASM_PFX(LoadFence)
> +ASM_PFX(LoadFence):
> + lfence
> + ret
> +
> diff --git a/MdePkg/Library/BaseLib/X64/LoadFence.nasm b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> new file mode 100644
> index 0000000000..c076d9789d
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> @@ -0,0 +1,38 @@
> +;------------------------------------------------------------------------------ ;
> +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +; This program and the accompanying materials
> +; are licensed and made available under the terms and conditions of the BSD License
> +; which accompanies this distribution. The full text of the license may be found at
> +; http://opensource.org/licenses/bsd-license.php.
> +;
> +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +;
> +; Module Name:
> +;
> +; LoadFence.nasm
> +;
> +; Abstract:
> +;
> +; Performs a serializing operation on all load-from-memory instructions that
> +; were issued prior to the call of this function.
> +;
> +; Notes:
> +;
> +;------------------------------------------------------------------------------
> +
> + DEFAULT REL
> + SECTION .text
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EFIAPI
> +; LoadFence (
> +; VOID
> +; );
> +;------------------------------------------------------------------------------
> +global ASM_PFX(LoadFence)
> +ASM_PFX(LoadFence):
> + lfence
> + ret
> +
>
Comments in no particular order:
(1) I think the EBC stub implementation should go into a separate file
under "MdePkg/Library/BaseLib/Ebc".
(2) Given that the ARM memory model is laxer than x86, I'm doubtful that
an empty implementation is appropriate. I expect a DMB variant should be
used, but I totally defer to Ard and Leif on that.
(3) We have Arm/ and AArch64/ subdirectories, but only one common
variant is provided, under Arm/. (I expect this fact (i.e., "common
variant") might remain true even after considering (2).) What I find
inconsistent though is that Ia32 and X64 get separate NASM files,
despite them sharing the implementation between each other as well.
IOW, this remark isn't about the actual implementation of the new API;
it's about consistency. If we decide for one ISA that the 32-bit and
64-bit platforms use a common set of files, then the other ISA (also
with 32-bit and 64-bit platforms) should act similarly, if a common
implementation is possible.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API
2018-09-20 13:13 ` Laszlo Ersek
@ 2018-09-21 2:14 ` Wu, Hao A
2018-09-21 2:21 ` Yao, Jiewen
2018-09-21 2:38 ` Wu, Hao A
1 sibling, 1 reply; 13+ messages in thread
From: Wu, Hao A @ 2018-09-21 2:14 UTC (permalink / raw)
To: Laszlo Ersek, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Yao, Jiewen, Gao, Liming
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Laszlo
> Ersek
> Sent: Thursday, September 20, 2018 9:13 PM
> To: Wu, Hao A; edk2-devel@lists.01.org
> Cc: Kinney, Michael D; Yao, Jiewen; Gao, Liming
> Subject: Re: [edk2] [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API
>
> On 09/20/18 08:40, Hao Wu wrote:
> > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1193
> >
> > This commit will add a new BaseLib API LoadFence(). This API will perform
> > a serializing operation on all load-from-memory instructions that were
> > issued prior to the call of this function.
> >
> > The purpose of adding this API is to mitigate of the [CVE-2017-5753]
> > Bounds Check Bypass issue when untrusted data are being processed within
> > SMM. More details can be referred at the 'Bounds check bypass mitigation'
> > section at the below link:
> >
> > https://software.intel.com/security-software-guidance/insights/host-
> firmware-speculative-execution-side-channel-mitigation
> >
> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Hao Wu <hao.a.wu@intel.com>
> > ---
> > MdePkg/Include/Library/BaseLib.h | 12 +++++++
> > MdePkg/Library/BaseLib/Arm/LoadFence.c | 26 ++++++++++++++
> > MdePkg/Library/BaseLib/BaseLib.inf | 4 +++
> > MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c | 15 +++++++-
> > MdePkg/Library/BaseLib/Ia32/LoadFence.nasm | 37 +++++++++++++++++++
> > MdePkg/Library/BaseLib/X64/LoadFence.nasm | 38
> ++++++++++++++++++++
> > 6 files changed, 131 insertions(+), 1 deletion(-)
> >
> > diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> > index 123ae19dc2..194726ca35 100644
> > --- a/MdePkg/Include/Library/BaseLib.h
> > +++ b/MdePkg/Include/Library/BaseLib.h
> > @@ -4939,6 +4939,18 @@ MemoryFence (
> >
> >
> > /**
> > + Performs a serializing operation on all load-from-memory instructions that
> > + were issued prior to the call of this function.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +LoadFence (
> > + VOID
> > + );
> > +
> > +
> > +/**
> > Saves the current CPU context that can be restored with a call to LongJump()
> > and returns 0.
> >
> > diff --git a/MdePkg/Library/BaseLib/Arm/LoadFence.c
> b/MdePkg/Library/BaseLib/Arm/LoadFence.c
> > new file mode 100644
> > index 0000000000..69f0c3a07e
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/Arm/LoadFence.c
> > @@ -0,0 +1,26 @@
> > +/** @file
> > + LoadFence() function for ARM.
> > +
> > + Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
> > +
> > + This program and the accompanying materials are licensed and made
> available
> > + under the terms and conditions of the BSD License which accompanies this
> > + distribution. The full text of the license may be found at
> > + http://opensource.org/licenses/bsd-license.php.
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS, WITHOUT
> > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> > +**/
> > +
> > +/**
> > + Performs a serializing operation on all load-from-memory instructions that
> > + were issued prior to the call of this function.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +LoadFence (
> > + VOID
> > + )
> > +{
> > +}
> > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> > index a1b5ec4b75..f028fbc75a 100644
> > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > @@ -68,6 +68,7 @@
> >
> > [Sources.Ia32]
> > Ia32/WriteTr.nasm
> > + Ia32/LoadFence.nasm
> >
> > Ia32/Wbinvd.c | MSFT
> > Ia32/WriteMm7.c | MSFT
> > @@ -346,6 +347,7 @@
> > X64/EnableCache.nasm
> > X64/DisableCache.nasm
> > X64/WriteTr.nasm
> > + X64/LoadFence.nasm
> >
> > X64/CpuBreakpoint.c | MSFT
> > X64/WriteMsr64.c | MSFT
> > @@ -580,6 +582,7 @@
> > [Sources.ARM]
> > Arm/InternalSwitchStack.c
> > Arm/Unaligned.c
> > + Arm/LoadFence.c
> > Math64.c | RVCT
> > Math64.c | MSFT
> >
> > @@ -613,6 +616,7 @@
> > [Sources.AARCH64]
> > Arm/InternalSwitchStack.c
> > Arm/Unaligned.c
> > + Arm/LoadFence.c
> > Math64.c
> >
> > AArch64/MemoryFence.S | GCC
> > diff --git a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > index 9b7d875664..a79461cfbf 100644
> > --- a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > +++ b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > @@ -1,7 +1,7 @@
> > /** @file
> > Base Library CPU Functions for EBC
> >
> > - Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
> > + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> > This program and the accompanying materials
> > are licensed and made available under the terms and conditions of the BSD
> License
> > which accompanies this distribution. The full text of the license may be
> found at
> > @@ -52,6 +52,19 @@ MemoryFence (
> > }
> >
> > /**
> > + Performs a serializing operation on all load-from-memory instructions that
> > + were issued prior to the call of this function.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +LoadFence (
> > + VOID
> > + )
> > +{
> > +}
> > +
> > +/**
> > Disables CPU interrupts.
> >
> > **/
> > diff --git a/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > new file mode 100644
> > index 0000000000..11600bea76
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > @@ -0,0 +1,37 @@
> > +;------------------------------------------------------------------------------ ;
> > +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> > +; This program and the accompanying materials
> > +; are licensed and made available under the terms and conditions of the BSD
> License
> > +; which accompanies this distribution. The full text of the license may be
> found at
> > +; http://opensource.org/licenses/bsd-license.php.
> > +;
> > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +;
> > +; Module Name:
> > +;
> > +; LoadFence.nasm
> > +;
> > +; Abstract:
> > +;
> > +; Performs a serializing operation on all load-from-memory instructions
> that
> > +; were issued prior to the call of this function.
> > +;
> > +; Notes:
> > +;
> > +;------------------------------------------------------------------------------
> > +
> > + SECTION .text
> > +
> > +;------------------------------------------------------------------------------
> > +; VOID
> > +; EFIAPI
> > +; LoadFence (
> > +; VOID
> > +; );
> > +;------------------------------------------------------------------------------
> > +global ASM_PFX(LoadFence)
> > +ASM_PFX(LoadFence):
> > + lfence
> > + ret
> > +
> > diff --git a/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> > new file mode 100644
> > index 0000000000..c076d9789d
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> > @@ -0,0 +1,38 @@
> > +;------------------------------------------------------------------------------ ;
> > +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> > +; This program and the accompanying materials
> > +; are licensed and made available under the terms and conditions of the BSD
> License
> > +; which accompanies this distribution. The full text of the license may be
> found at
> > +; http://opensource.org/licenses/bsd-license.php.
> > +;
> > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +;
> > +; Module Name:
> > +;
> > +; LoadFence.nasm
> > +;
> > +; Abstract:
> > +;
> > +; Performs a serializing operation on all load-from-memory instructions
> that
> > +; were issued prior to the call of this function.
> > +;
> > +; Notes:
> > +;
> > +;------------------------------------------------------------------------------
> > +
> > + DEFAULT REL
> > + SECTION .text
> > +
> > +;------------------------------------------------------------------------------
> > +; VOID
> > +; EFIAPI
> > +; LoadFence (
> > +; VOID
> > +; );
> > +;------------------------------------------------------------------------------
> > +global ASM_PFX(LoadFence)
> > +ASM_PFX(LoadFence):
> > + lfence
> > + ret
> > +
> >
>
> Comments in no particular order:
>
> (1) I think the EBC stub implementation should go into a separate file
> under "MdePkg/Library/BaseLib/Ebc".
Yes, I will do this in later version of the series.
>
> (2) Given that the ARM memory model is laxer than x86, I'm doubtful that
> an empty implementation is appropriate. I expect a DMB variant should be
> used, but I totally defer to Ard and Leif on that.
>
> (3) We have Arm/ and AArch64/ subdirectories, but only one common
> variant is provided, under Arm/. (I expect this fact (i.e., "common
> variant") might remain true even after considering (2).) What I find
> inconsistent though is that Ia32 and X64 get separate NASM files,
> despite them sharing the implementation between each other as well.
Thanks for the comments.
I will start a new discussion to loop in Ard and Leif to have a discussion
on this.
Best Regards,
Hao Wu
>
> IOW, this remark isn't about the actual implementation of the new API;
> it's about consistency. If we decide for one ISA that the 32-bit and
> 64-bit platforms use a common set of files, then the other ISA (also
> with 32-bit and 64-bit platforms) should act similarly, if a common
> implementation is possible.
>
> Thanks
> Laszlo
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API
2018-09-21 2:14 ` Wu, Hao A
@ 2018-09-21 2:21 ` Yao, Jiewen
0 siblings, 0 replies; 13+ messages in thread
From: Yao, Jiewen @ 2018-09-21 2:21 UTC (permalink / raw)
To: Wu, Hao A, Laszlo Ersek, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Gao, Liming
Thanks Laszlo.
That is very good feedback. For ARM, I think we need use *CSDB*. :-)
Thank you
Yao Jiewen
> -----Original Message-----
> From: Wu, Hao A
> Sent: Friday, September 21, 2018 10:15 AM
> To: Laszlo Ersek <lersek@redhat.com>; edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Yao, Jiewen
> <jiewen.yao@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: RE: [edk2] [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Laszlo
> > Ersek
> > Sent: Thursday, September 20, 2018 9:13 PM
> > To: Wu, Hao A; edk2-devel@lists.01.org
> > Cc: Kinney, Michael D; Yao, Jiewen; Gao, Liming
> > Subject: Re: [edk2] [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence
> API
> >
> > On 09/20/18 08:40, Hao Wu wrote:
> > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1193
> > >
> > > This commit will add a new BaseLib API LoadFence(). This API will
> perform
> > > a serializing operation on all load-from-memory instructions that were
> > > issued prior to the call of this function.
> > >
> > > The purpose of adding this API is to mitigate of the [CVE-2017-5753]
> > > Bounds Check Bypass issue when untrusted data are being processed
> within
> > > SMM. More details can be referred at the 'Bounds check bypass
> mitigation'
> > > section at the below link:
> > >
> > > https://software.intel.com/security-software-guidance/insights/host-
> > firmware-speculative-execution-side-channel-mitigation
> > >
> > > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > > Cc: Laszlo Ersek <lersek@redhat.com>
> > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > > Cc: Liming Gao <liming.gao@intel.com>
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Hao Wu <hao.a.wu@intel.com>
> > > ---
> > > MdePkg/Include/Library/BaseLib.h | 12 +++++++
> > > MdePkg/Library/BaseLib/Arm/LoadFence.c | 26 ++++++++++++++
> > > MdePkg/Library/BaseLib/BaseLib.inf | 4 +++
> > > MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c | 15 +++++++-
> > > MdePkg/Library/BaseLib/Ia32/LoadFence.nasm | 37
> +++++++++++++++++++
> > > MdePkg/Library/BaseLib/X64/LoadFence.nasm | 38
> > ++++++++++++++++++++
> > > 6 files changed, 131 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/MdePkg/Include/Library/BaseLib.h
> > b/MdePkg/Include/Library/BaseLib.h
> > > index 123ae19dc2..194726ca35 100644
> > > --- a/MdePkg/Include/Library/BaseLib.h
> > > +++ b/MdePkg/Include/Library/BaseLib.h
> > > @@ -4939,6 +4939,18 @@ MemoryFence (
> > >
> > >
> > > /**
> > > + Performs a serializing operation on all load-from-memory
> instructions that
> > > + were issued prior to the call of this function.
> > > +
> > > +**/
> > > +VOID
> > > +EFIAPI
> > > +LoadFence (
> > > + VOID
> > > + );
> > > +
> > > +
> > > +/**
> > > Saves the current CPU context that can be restored with a call to
> LongJump()
> > > and returns 0.
> > >
> > > diff --git a/MdePkg/Library/BaseLib/Arm/LoadFence.c
> > b/MdePkg/Library/BaseLib/Arm/LoadFence.c
> > > new file mode 100644
> > > index 0000000000..69f0c3a07e
> > > --- /dev/null
> > > +++ b/MdePkg/Library/BaseLib/Arm/LoadFence.c
> > > @@ -0,0 +1,26 @@
> > > +/** @file
> > > + LoadFence() function for ARM.
> > > +
> > > + Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
> > > +
> > > + This program and the accompanying materials are licensed and made
> > available
> > > + under the terms and conditions of the BSD License which
> accompanies this
> > > + distribution. The full text of the license may be found at
> > > + http://opensource.org/licenses/bsd-license.php.
> > > +
> > > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> > BASIS, WITHOUT
> > > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
> OR
> > IMPLIED.
> > > +**/
> > > +
> > > +/**
> > > + Performs a serializing operation on all load-from-memory
> instructions that
> > > + were issued prior to the call of this function.
> > > +
> > > +**/
> > > +VOID
> > > +EFIAPI
> > > +LoadFence (
> > > + VOID
> > > + )
> > > +{
> > > +}
> > > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> > b/MdePkg/Library/BaseLib/BaseLib.inf
> > > index a1b5ec4b75..f028fbc75a 100644
> > > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > > @@ -68,6 +68,7 @@
> > >
> > > [Sources.Ia32]
> > > Ia32/WriteTr.nasm
> > > + Ia32/LoadFence.nasm
> > >
> > > Ia32/Wbinvd.c | MSFT
> > > Ia32/WriteMm7.c | MSFT
> > > @@ -346,6 +347,7 @@
> > > X64/EnableCache.nasm
> > > X64/DisableCache.nasm
> > > X64/WriteTr.nasm
> > > + X64/LoadFence.nasm
> > >
> > > X64/CpuBreakpoint.c | MSFT
> > > X64/WriteMsr64.c | MSFT
> > > @@ -580,6 +582,7 @@
> > > [Sources.ARM]
> > > Arm/InternalSwitchStack.c
> > > Arm/Unaligned.c
> > > + Arm/LoadFence.c
> > > Math64.c | RVCT
> > > Math64.c | MSFT
> > >
> > > @@ -613,6 +616,7 @@
> > > [Sources.AARCH64]
> > > Arm/InternalSwitchStack.c
> > > Arm/Unaligned.c
> > > + Arm/LoadFence.c
> > > Math64.c
> > >
> > > AArch64/MemoryFence.S | GCC
> > > diff --git a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > > index 9b7d875664..a79461cfbf 100644
> > > --- a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > > +++ b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > > @@ -1,7 +1,7 @@
> > > /** @file
> > > Base Library CPU Functions for EBC
> > >
> > > - Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
> > > + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> > > This program and the accompanying materials
> > > are licensed and made available under the terms and conditions of
> the BSD
> > License
> > > which accompanies this distribution. The full text of the license
> may be
> > found at
> > > @@ -52,6 +52,19 @@ MemoryFence (
> > > }
> > >
> > > /**
> > > + Performs a serializing operation on all load-from-memory
> instructions that
> > > + were issued prior to the call of this function.
> > > +
> > > +**/
> > > +VOID
> > > +EFIAPI
> > > +LoadFence (
> > > + VOID
> > > + )
> > > +{
> > > +}
> > > +
> > > +/**
> > > Disables CPU interrupts.
> > >
> > > **/
> > > diff --git a/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > > new file mode 100644
> > > index 0000000000..11600bea76
> > > --- /dev/null
> > > +++ b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > > @@ -0,0 +1,37 @@
> > > +;------------------------------------------------------------------------------ ;
> > > +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> > > +; This program and the accompanying materials
> > > +; are licensed and made available under the terms and conditions of the
> BSD
> > License
> > > +; which accompanies this distribution. The full text of the license may
> be
> > found at
> > > +; http://opensource.org/licenses/bsd-license.php.
> > > +;
> > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> > BASIS,
> > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > EXPRESS OR IMPLIED.
> > > +;
> > > +; Module Name:
> > > +;
> > > +; LoadFence.nasm
> > > +;
> > > +; Abstract:
> > > +;
> > > +; Performs a serializing operation on all load-from-memory
> instructions
> > that
> > > +; were issued prior to the call of this function.
> > > +;
> > > +; Notes:
> > > +;
> > > +;------------------------------------------------------------------------------
> > > +
> > > + SECTION .text
> > > +
> > > +;------------------------------------------------------------------------------
> > > +; VOID
> > > +; EFIAPI
> > > +; LoadFence (
> > > +; VOID
> > > +; );
> > > +;------------------------------------------------------------------------------
> > > +global ASM_PFX(LoadFence)
> > > +ASM_PFX(LoadFence):
> > > + lfence
> > > + ret
> > > +
> > > diff --git a/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> > b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> > > new file mode 100644
> > > index 0000000000..c076d9789d
> > > --- /dev/null
> > > +++ b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> > > @@ -0,0 +1,38 @@
> > > +;------------------------------------------------------------------------------ ;
> > > +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> > > +; This program and the accompanying materials
> > > +; are licensed and made available under the terms and conditions of the
> BSD
> > License
> > > +; which accompanies this distribution. The full text of the license may
> be
> > found at
> > > +; http://opensource.org/licenses/bsd-license.php.
> > > +;
> > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> > BASIS,
> > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > EXPRESS OR IMPLIED.
> > > +;
> > > +; Module Name:
> > > +;
> > > +; LoadFence.nasm
> > > +;
> > > +; Abstract:
> > > +;
> > > +; Performs a serializing operation on all load-from-memory
> instructions
> > that
> > > +; were issued prior to the call of this function.
> > > +;
> > > +; Notes:
> > > +;
> > > +;------------------------------------------------------------------------------
> > > +
> > > + DEFAULT REL
> > > + SECTION .text
> > > +
> > > +;------------------------------------------------------------------------------
> > > +; VOID
> > > +; EFIAPI
> > > +; LoadFence (
> > > +; VOID
> > > +; );
> > > +;------------------------------------------------------------------------------
> > > +global ASM_PFX(LoadFence)
> > > +ASM_PFX(LoadFence):
> > > + lfence
> > > + ret
> > > +
> > >
> >
> > Comments in no particular order:
> >
> > (1) I think the EBC stub implementation should go into a separate file
> > under "MdePkg/Library/BaseLib/Ebc".
>
> Yes, I will do this in later version of the series.
>
> >
> > (2) Given that the ARM memory model is laxer than x86, I'm doubtful that
> > an empty implementation is appropriate. I expect a DMB variant should be
> > used, but I totally defer to Ard and Leif on that.
> >
> > (3) We have Arm/ and AArch64/ subdirectories, but only one common
> > variant is provided, under Arm/. (I expect this fact (i.e., "common
> > variant") might remain true even after considering (2).) What I find
> > inconsistent though is that Ia32 and X64 get separate NASM files,
> > despite them sharing the implementation between each other as well.
>
> Thanks for the comments.
> I will start a new discussion to loop in Ard and Leif to have a discussion
> on this.
>
> Best Regards,
> Hao Wu
>
> >
> > IOW, this remark isn't about the actual implementation of the new API;
> > it's about consistency. If we decide for one ISA that the 32-bit and
> > 64-bit platforms use a common set of files, then the other ISA (also
> > with 32-bit and 64-bit platforms) should act similarly, if a common
> > implementation is possible.
> >
> > Thanks
> > Laszlo
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API
2018-09-20 13:13 ` Laszlo Ersek
2018-09-21 2:14 ` Wu, Hao A
@ 2018-09-21 2:38 ` Wu, Hao A
1 sibling, 0 replies; 13+ messages in thread
From: Wu, Hao A @ 2018-09-21 2:38 UTC (permalink / raw)
To: Ard Biesheuvel, Leif Lindholm, Laszlo Ersek,
edk2-devel@lists.01.org
Cc: Kinney, Michael D, Yao, Jiewen, Gao, Liming
Hi Ard and Leif,
This commit aims to add to a new BaseLib API to implement the serializing
load operations functionality (for IA32/X64, called LFENCE).
For the 1st version of this commit, this API is named as 'LoadFence'. The
implementation only covers IA32/X64 arch, and does an empty implementation
for ARM/AARCH64.
But as Laszlo pointed out (comment (2) below), the empty implementation
for ARM/AARCH64 may be inappropriate, I would like to turn to you for some
helps or suggestions on the implementation of this API.
Also, as Laszlo pointed out in his comment (3) below, if the
implementations between ARM & AARCH64 are the same (not sure if this is
the case, I am not very familiar with ARM instructions). Do you have
comments or preference on the location of the codes?
A) Duplicate implementations under BaseLib\Arm and BaseLib\AArch64
(Like the IA32 & X64 implementation)
B) Use one common implementation under BaseLib\Arm
Thanks in advance.
Best Regards,
Hao Wu
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Laszlo
> Ersek
> Sent: Thursday, September 20, 2018 9:13 PM
> To: Wu, Hao A; edk2-devel@lists.01.org
> Cc: Kinney, Michael D; Yao, Jiewen; Gao, Liming
> Subject: Re: [edk2] [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API
>
> On 09/20/18 08:40, Hao Wu wrote:
> > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1193
> >
> > This commit will add a new BaseLib API LoadFence(). This API will perform
> > a serializing operation on all load-from-memory instructions that were
> > issued prior to the call of this function.
> >
> > The purpose of adding this API is to mitigate of the [CVE-2017-5753]
> > Bounds Check Bypass issue when untrusted data are being processed within
> > SMM. More details can be referred at the 'Bounds check bypass mitigation'
> > section at the below link:
> >
> > https://software.intel.com/security-software-guidance/insights/host-
> firmware-speculative-execution-side-channel-mitigation
> >
> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Hao Wu <hao.a.wu@intel.com>
> > ---
> > MdePkg/Include/Library/BaseLib.h | 12 +++++++
> > MdePkg/Library/BaseLib/Arm/LoadFence.c | 26 ++++++++++++++
> > MdePkg/Library/BaseLib/BaseLib.inf | 4 +++
> > MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c | 15 +++++++-
> > MdePkg/Library/BaseLib/Ia32/LoadFence.nasm | 37 +++++++++++++++++++
> > MdePkg/Library/BaseLib/X64/LoadFence.nasm | 38
> ++++++++++++++++++++
> > 6 files changed, 131 insertions(+), 1 deletion(-)
> >
> > diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> > index 123ae19dc2..194726ca35 100644
> > --- a/MdePkg/Include/Library/BaseLib.h
> > +++ b/MdePkg/Include/Library/BaseLib.h
> > @@ -4939,6 +4939,18 @@ MemoryFence (
> >
> >
> > /**
> > + Performs a serializing operation on all load-from-memory instructions that
> > + were issued prior to the call of this function.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +LoadFence (
> > + VOID
> > + );
> > +
> > +
> > +/**
> > Saves the current CPU context that can be restored with a call to LongJump()
> > and returns 0.
> >
> > diff --git a/MdePkg/Library/BaseLib/Arm/LoadFence.c
> b/MdePkg/Library/BaseLib/Arm/LoadFence.c
> > new file mode 100644
> > index 0000000000..69f0c3a07e
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/Arm/LoadFence.c
> > @@ -0,0 +1,26 @@
> > +/** @file
> > + LoadFence() function for ARM.
> > +
> > + Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
> > +
> > + This program and the accompanying materials are licensed and made
> available
> > + under the terms and conditions of the BSD License which accompanies this
> > + distribution. The full text of the license may be found at
> > + http://opensource.org/licenses/bsd-license.php.
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS, WITHOUT
> > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> > +**/
> > +
> > +/**
> > + Performs a serializing operation on all load-from-memory instructions that
> > + were issued prior to the call of this function.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +LoadFence (
> > + VOID
> > + )
> > +{
> > +}
> > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> > index a1b5ec4b75..f028fbc75a 100644
> > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > @@ -68,6 +68,7 @@
> >
> > [Sources.Ia32]
> > Ia32/WriteTr.nasm
> > + Ia32/LoadFence.nasm
> >
> > Ia32/Wbinvd.c | MSFT
> > Ia32/WriteMm7.c | MSFT
> > @@ -346,6 +347,7 @@
> > X64/EnableCache.nasm
> > X64/DisableCache.nasm
> > X64/WriteTr.nasm
> > + X64/LoadFence.nasm
> >
> > X64/CpuBreakpoint.c | MSFT
> > X64/WriteMsr64.c | MSFT
> > @@ -580,6 +582,7 @@
> > [Sources.ARM]
> > Arm/InternalSwitchStack.c
> > Arm/Unaligned.c
> > + Arm/LoadFence.c
> > Math64.c | RVCT
> > Math64.c | MSFT
> >
> > @@ -613,6 +616,7 @@
> > [Sources.AARCH64]
> > Arm/InternalSwitchStack.c
> > Arm/Unaligned.c
> > + Arm/LoadFence.c
> > Math64.c
> >
> > AArch64/MemoryFence.S | GCC
> > diff --git a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > index 9b7d875664..a79461cfbf 100644
> > --- a/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > +++ b/MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > @@ -1,7 +1,7 @@
> > /** @file
> > Base Library CPU Functions for EBC
> >
> > - Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
> > + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> > This program and the accompanying materials
> > are licensed and made available under the terms and conditions of the BSD
> License
> > which accompanies this distribution. The full text of the license may be
> found at
> > @@ -52,6 +52,19 @@ MemoryFence (
> > }
> >
> > /**
> > + Performs a serializing operation on all load-from-memory instructions that
> > + were issued prior to the call of this function.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +LoadFence (
> > + VOID
> > + )
> > +{
> > +}
> > +
> > +/**
> > Disables CPU interrupts.
> >
> > **/
> > diff --git a/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > new file mode 100644
> > index 0000000000..11600bea76
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > @@ -0,0 +1,37 @@
> > +;------------------------------------------------------------------------------ ;
> > +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> > +; This program and the accompanying materials
> > +; are licensed and made available under the terms and conditions of the BSD
> License
> > +; which accompanies this distribution. The full text of the license may be
> found at
> > +; http://opensource.org/licenses/bsd-license.php.
> > +;
> > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +;
> > +; Module Name:
> > +;
> > +; LoadFence.nasm
> > +;
> > +; Abstract:
> > +;
> > +; Performs a serializing operation on all load-from-memory instructions
> that
> > +; were issued prior to the call of this function.
> > +;
> > +; Notes:
> > +;
> > +;------------------------------------------------------------------------------
> > +
> > + SECTION .text
> > +
> > +;------------------------------------------------------------------------------
> > +; VOID
> > +; EFIAPI
> > +; LoadFence (
> > +; VOID
> > +; );
> > +;------------------------------------------------------------------------------
> > +global ASM_PFX(LoadFence)
> > +ASM_PFX(LoadFence):
> > + lfence
> > + ret
> > +
> > diff --git a/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> > new file mode 100644
> > index 0000000000..c076d9789d
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/X64/LoadFence.nasm
> > @@ -0,0 +1,38 @@
> > +;------------------------------------------------------------------------------ ;
> > +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> > +; This program and the accompanying materials
> > +; are licensed and made available under the terms and conditions of the BSD
> License
> > +; which accompanies this distribution. The full text of the license may be
> found at
> > +; http://opensource.org/licenses/bsd-license.php.
> > +;
> > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +;
> > +; Module Name:
> > +;
> > +; LoadFence.nasm
> > +;
> > +; Abstract:
> > +;
> > +; Performs a serializing operation on all load-from-memory instructions
> that
> > +; were issued prior to the call of this function.
> > +;
> > +; Notes:
> > +;
> > +;------------------------------------------------------------------------------
> > +
> > + DEFAULT REL
> > + SECTION .text
> > +
> > +;------------------------------------------------------------------------------
> > +; VOID
> > +; EFIAPI
> > +; LoadFence (
> > +; VOID
> > +; );
> > +;------------------------------------------------------------------------------
> > +global ASM_PFX(LoadFence)
> > +ASM_PFX(LoadFence):
> > + lfence
> > + ret
> > +
> >
>
> Comments in no particular order:
>
> (1) I think the EBC stub implementation should go into a separate file
> under "MdePkg/Library/BaseLib/Ebc".
>
> (2) Given that the ARM memory model is laxer than x86, I'm doubtful that
> an empty implementation is appropriate. I expect a DMB variant should be
> used, but I totally defer to Ard and Leif on that.
>
> (3) We have Arm/ and AArch64/ subdirectories, but only one common
> variant is provided, under Arm/. (I expect this fact (i.e., "common
> variant") might remain true even after considering (2).) What I find
> inconsistent though is that Ia32 and X64 get separate NASM files,
> despite them sharing the implementation between each other as well.
>
> IOW, this remark isn't about the actual implementation of the new API;
> it's about consistency. If we decide for one ISA that the 32-bit and
> 64-bit platforms use a common set of files, then the other ISA (also
> with 32-bit and 64-bit platforms) should act similarly, if a common
> implementation is possible.
>
> Thanks
> Laszlo
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v1 2/5] MdeModulePkg/FaultTolerantWrite:[CVE-2017-5753]Fix bounds check bypass
2018-09-20 6:40 [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Hao Wu
2018-09-20 6:40 ` [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API Hao Wu
@ 2018-09-20 6:41 ` Hao Wu
2018-09-20 6:41 ` [PATCH v1 3/5] MdeModulePkg/SmmLockBox: [CVE-2017-5753] Fix " Hao Wu
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Hao Wu @ 2018-09-20 6:41 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Jiewen Yao, Star Zeng
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1194
Speculative execution is used by processor to avoid having to wait for
data to arrive from memory, or for previous operations to finish, the
processor may speculate as to what will be executed.
If the speculation is incorrect, the speculatively executed instructions
might leave hints such as which memory locations have been brought into
cache. Malicious actors can use the bounds check bypass method (code
gadgets with controlled external inputs) to infer data values that have
been used in speculative operations to reveal secrets which should not
otherwise be accessed.
This commit will focus on the SMI handler(s) registered within the
FaultTolerantWriteDxe driver and insert LoadFence API to mitigate the
bounds check bypass issue.
For SMI handler SmmFaultTolerantWriteHandler():
Under "case FTW_FUNCTION_WRITE:", 'SmmFtwWriteHeader->Length' can be a
potential cross boundary access of the 'CommBuffer' (controlled external
inputs) during speculative execution. This cross boundary access is later
passed as parameter 'Length' into function FtwWrite().
Within function FtwWrite(), the value of 'Length' can be inferred by code:
"CopyMem (MyBuffer + Offset, Buffer, Length);". One can observe which part
of the content within 'Buffer' was brought into cache to possibly reveal
the value of 'Length'.
Hence, this commit adds a LoadFence after the boundary/range checks of
'CommBuffer' to prevent the speculative execution.
A more detailed explanation of the purpose of commit is under the
'Bounds check bypass mitigation' section of the below link:
https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation
And the document at:
https://software.intel.com/security-software-guidance/api-app/sites/default/files/337879-analyzing-potential-bounds-Check-bypass-vulnerabilities.pdf
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.c | 2 ++
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf | 1 +
2 files changed, 3 insertions(+)
diff --git a/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.c b/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.c
index 632313f076..2ed1bb9498 100644
--- a/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.c
+++ b/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.c
@@ -57,6 +57,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <PiSmm.h>
#include <Library/SmmServicesTableLib.h>
#include <Library/SmmMemLib.h>
+#include <Library/BaseLib.h>
#include <Protocol/SmmSwapAddressRange.h>
#include "FaultTolerantWrite.h"
#include "FaultTolerantWriteSmmCommon.h"
@@ -417,6 +418,7 @@ SmmFaultTolerantWriteHandler (
&SmmFvbHandle
);
if (!EFI_ERROR (Status)) {
+ LoadFence ();
Status = FtwWrite(
&mFtwDevice->FtwInstance,
SmmFtwWriteHeader->Lba,
diff --git a/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf b/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
index 85d109e8d9..606cc2266b 100644
--- a/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+++ b/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
@@ -55,6 +55,7 @@
PcdLib
ReportStatusCodeLib
SmmMemLib
+ BaseLib
[Guids]
#
--
2.12.0.windows.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 3/5] MdeModulePkg/SmmLockBox: [CVE-2017-5753] Fix bounds check bypass
2018-09-20 6:40 [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Hao Wu
2018-09-20 6:40 ` [PATCH v1 1/5] MdePkg/BaseLib: Add new LoadFence API Hao Wu
2018-09-20 6:41 ` [PATCH v1 2/5] MdeModulePkg/FaultTolerantWrite:[CVE-2017-5753]Fix bounds check bypass Hao Wu
@ 2018-09-20 6:41 ` Hao Wu
2018-09-20 6:41 ` [PATCH v1 4/5] MdeModulePkg/Variable: " Hao Wu
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Hao Wu @ 2018-09-20 6:41 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Jiewen Yao, Star Zeng
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1194
Speculative execution is used by processor to avoid having to wait for
data to arrive from memory, or for previous operations to finish, the
processor may speculate as to what will be executed.
If the speculation is incorrect, the speculatively executed instructions
might leave hints such as which memory locations have been brought into
cache. Malicious actors can use the bounds check bypass method (code
gadgets with controlled external inputs) to infer data values that have
been used in speculative operations to reveal secrets which should not
otherwise be accessed.
This commit will focus on the SMI handler(s) registered within the
SmmLockBox driver and insert LoadFence API to mitigate the
bounds check bypass issue.
For SMI handler SmmLockBoxHandler():
Under "case EFI_SMM_LOCK_BOX_COMMAND_SAVE:", the 'CommBuffer' (controlled
external inputs) is passed to function SmmLockBoxSave().
'TempLockBoxParameterSave.Length' can be a potential cross boundary access
of the 'CommBuffer' during speculative execution. This cross boundary
access is later passed as parameter 'Length' into function SaveLockBox().
Within function SaveLockBox(), the value of 'Length' can be inferred by
code:
"CopyMem ((VOID *)(UINTN)SmramBuffer, (VOID *)(UINTN)Buffer, Length);".
One can observe which part of the content within 'Buffer' was brought into
cache to possibly reveal the value of 'Length'.
Hence, this commit adds a LoadFence after the boundary/range checks of
'CommBuffer' to prevent the speculative execution.
And there is a similar case under "case EFI_SMM_LOCK_BOX_COMMAND_UPDATE:"
function SmmLockBoxUpdate() as well. This commits also handles it.
A more detailed explanation of the purpose of commit is under the
'Bounds check bypass mitigation' section of the below link:
https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation
And the document at:
https://software.intel.com/security-software-guidance/api-app/sites/default/files/337879-analyzing-potential-bounds-Check-bypass-vulnerabilities.pdf
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.c b/MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.c
index 5a11743cb9..87b4947908 100644
--- a/MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.c
+++ b/MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.c
@@ -76,6 +76,7 @@ SmmLockBoxSave (
LockBoxParameterSave->Header.ReturnStatus = (UINT64)EFI_ACCESS_DENIED;
return ;
}
+ LoadFence ();
//
// Save data
@@ -160,6 +161,7 @@ SmmLockBoxUpdate (
LockBoxParameterUpdate->Header.ReturnStatus = (UINT64)EFI_ACCESS_DENIED;
return ;
}
+ LoadFence ();
//
// Update data
--
2.12.0.windows.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 4/5] MdeModulePkg/Variable: [CVE-2017-5753] Fix bounds check bypass
2018-09-20 6:40 [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Hao Wu
` (2 preceding siblings ...)
2018-09-20 6:41 ` [PATCH v1 3/5] MdeModulePkg/SmmLockBox: [CVE-2017-5753] Fix " Hao Wu
@ 2018-09-20 6:41 ` Hao Wu
2018-09-20 6:41 ` [PATCH v1 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: " Hao Wu
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Hao Wu @ 2018-09-20 6:41 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Jiewen Yao, Star Zeng
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1194
Speculative execution is used by processor to avoid having to wait for
data to arrive from memory, or for previous operations to finish, the
processor may speculate as to what will be executed.
If the speculation is incorrect, the speculatively executed instructions
might leave hints such as which memory locations have been brought into
cache. Malicious actors can use the bounds check bypass method (code
gadgets with controlled external inputs) to infer data values that have
been used in speculative operations to reveal secrets which should not
otherwise be accessed.
This commit will focus on the SMI handler(s) registered within the
Variable\RuntimeDxe driver and insert LoadFence API to mitigate the
bounds check bypass issue.
For SMI handler SmmVariableHandler():
Under "case SMM_VARIABLE_FUNCTION_GET_VARIABLE:",
'SmmVariableHeader->NameSize' can be a potential cross boundary access of
the 'CommBuffer' (controlled external input) during speculative execution.
This cross boundary access is later used as the index to access array
'SmmVariableHeader->Name' by code:
"SmmVariableHeader->Name[SmmVariableHeader->NameSize/sizeof (CHAR16) - 1]"
One can observe which part of the content within array was brought into
cache to possibly reveal the value of 'SmmVariableHeader->NameSize'.
Hence, this commit adds a LoadFence after the boundary/range checks of
'CommBuffer' to prevent the speculative execution.
And there are 2 similar cases under
"case SMM_VARIABLE_FUNCTION_SET_VARIABLE:" and
"case SMM_VARIABLE_FUNCTION_VAR_CHECK_VARIABLE_PROPERTY_GET:" as well.
This commits also handles them.
Also, under "case SMM_VARIABLE_FUNCTION_SET_VARIABLE:",
'(UINT8 *)SmmVariableHeader->Name + SmmVariableHeader->NameSize' points to
the 'CommBuffer' (with some offset) and then passed as parameter 'Data' to
function VariableServiceSetVariable().
Within function VariableServiceSetVariable(), there is a sanity check for
EFI_VARIABLE_AUTHENTICATION_2 descriptor for the data pointed by 'Data'.
If this check is speculatively bypassed, potential cross-boundary data
access for 'Data' is possible to be revealed via the below function calls
sequence during speculative execution:
AuthVariableLibProcessVariable()
ProcessVarWithPk() or ProcessVarWithKek()
Within function ProcessVarWithPk() or ProcessVarWithKek(), for the code
"PayloadSize = DataSize - AUTHINFO2_SIZE (Data);", 'AUTHINFO2_SIZE (Data)'
can be a cross boundary access during speculative execution.
Then, 'PayloadSize' is possible to be revealed by the function call
sequence:
AuthServiceInternalUpdateVariableWithTimeStamp()
mAuthVarLibContextIn->UpdateVariable()
VariableExLibUpdateVariable()
UpdateVariable()
CopyMem()
Hence, this commit adds a LoadFence after the sanity check for
EFI_VARIABLE_AUTHENTICATION_2 descriptor upon 'Data' within function
VariableServiceSetVariable() to prevent the speculative execution.
A more detailed explanation of the purpose of commit is under the
'Bounds check bypass mitigation' section of the below link:
https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation
And the document at:
https://software.intel.com/security-software-guidance/api-app/sites/default/files/337879-analyzing-potential-bounds-Check-bypass-vulnerabilities.pdf
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c | 1 +
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c b/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
index 1ea2f84dda..52af56c4c0 100644
--- a/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
+++ b/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
@@ -3198,6 +3198,7 @@ VariableServiceSetVariable (
((EFI_VARIABLE_AUTHENTICATION_2 *) Data)->AuthInfo.Hdr.dwLength < OFFSET_OF (WIN_CERTIFICATE_UEFI_GUID, CertData)) {
return EFI_SECURITY_VIOLATION;
}
+ LoadFence ();
PayloadSize = DataSize - AUTHINFO2_SIZE (Data);
} else {
PayloadSize = DataSize;
diff --git a/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.c b/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.c
index e495d971a0..0bbed71a76 100644
--- a/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.c
+++ b/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.c
@@ -537,6 +537,7 @@ SmmVariableHandler (
goto EXIT;
}
+ LoadFence ();
if (SmmVariableHeader->NameSize < sizeof (CHAR16) || SmmVariableHeader->Name[SmmVariableHeader->NameSize/sizeof (CHAR16) - 1] != L'\0') {
//
// Make sure VariableName is A Null-terminated string.
@@ -631,6 +632,7 @@ SmmVariableHandler (
goto EXIT;
}
+ LoadFence ();
if (SmmVariableHeader->NameSize < sizeof (CHAR16) || SmmVariableHeader->Name[SmmVariableHeader->NameSize/sizeof (CHAR16) - 1] != L'\0') {
//
// Make sure VariableName is A Null-terminated string.
@@ -766,6 +768,7 @@ SmmVariableHandler (
goto EXIT;
}
+ LoadFence ();
if (CommVariableProperty->NameSize < sizeof (CHAR16) || CommVariableProperty->Name[CommVariableProperty->NameSize/sizeof (CHAR16) - 1] != L'\0') {
//
// Make sure VariableName is A Null-terminated string.
--
2.12.0.windows.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5753] Fix bounds check bypass
2018-09-20 6:40 [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Hao Wu
` (3 preceding siblings ...)
2018-09-20 6:41 ` [PATCH v1 4/5] MdeModulePkg/Variable: " Hao Wu
@ 2018-09-20 6:41 ` Hao Wu
2018-09-20 13:22 ` [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Laszlo Ersek
2018-09-20 13:59 ` Kinney, Michael D
6 siblings, 0 replies; 13+ messages in thread
From: Hao Wu @ 2018-09-20 6:41 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Laszlo Ersek, Jiewen Yao, Michael D Kinney, Eric Dong
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1194
Speculative execution is used by processor to avoid having to wait for
data to arrive from memory, or for previous operations to finish, the
processor may speculate as to what will be executed.
If the speculation is incorrect, the speculatively executed instructions
might leave hints such as which memory locations have been brought into
cache. Malicious actors can use the bounds check bypass method (code
gadgets with controlled external inputs) to infer data values that have
been used in speculative operations to reveal secrets which should not
otherwise be accessed.
It is possible for SMI handler(s) to call EFI_SMM_CPU_PROTOCOL service
ReadSaveState() and use the content in the 'CommBuffer' (controlled
external inputs) as the 'CpuIndex'. So this commit will insert LoadFence
API to mitigate the bounds check bypass issue within SmmReadSaveState().
For SmmReadSaveState():
The 'CpuIndex' will be passed into function ReadSaveStateRegister(). And
then in to ReadSaveStateRegisterByIndex().
With the call:
ReadSaveStateRegisterByIndex (
CpuIndex,
SMM_SAVE_STATE_REGISTER_IOMISC_INDEX,
sizeof(IoMisc.Uint32),
&IoMisc.Uint32
);
The 'IoMisc' can be a cross boundary access during speculative execution.
Later, 'IoMisc' is used as the index to access buffers 'mSmmCpuIoWidth'
and 'mSmmCpuIoType'. One can observe which part of the content within
those buffers was brought into cache to possibly reveal the value of
'IoMisc'.
Hence, this commit adds a LoadFence after the check of 'CpuIndex' within
function SmmReadSaveState() to prevent the speculative execution.
A more detailed explanation of the purpose of commit is under the
'Bounds check bypass mitigation' section of the below link:
https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation
And the document at:
https://software.intel.com/security-software-guidance/api-app/sites/default/files/337879-analyzing-potential-bounds-Check-bypass-vulnerabilities.pdf
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index fbf74e8d90..256a8bbb94 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -237,6 +237,7 @@ SmmReadSaveState (
if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
+ LoadFence ();
//
// Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
--
2.12.0.windows.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers
2018-09-20 6:40 [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Hao Wu
` (4 preceding siblings ...)
2018-09-20 6:41 ` [PATCH v1 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: " Hao Wu
@ 2018-09-20 13:22 ` Laszlo Ersek
2018-09-20 13:59 ` Kinney, Michael D
6 siblings, 0 replies; 13+ messages in thread
From: Laszlo Ersek @ 2018-09-20 13:22 UTC (permalink / raw)
To: Hao Wu, edk2-devel
Cc: Eric Dong, Liming Gao, Jiewen Yao, Michael D Kinney, Star Zeng
On 09/20/18 08:40, Hao Wu wrote:
> The series aims to mitigate the Bounds Check Bypass (CVE-2017-5753) issues
> within SMI handlers.
>
> A more detailed explanation of the purpose of the series is under the
> 'Bounds check bypass mitigation' section of the below link:
> https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation
>
> And the document at:
> https://software.intel.com/security-software-guidance/api-app/sites/default/files/337879-analyzing-potential-bounds-Check-bypass-vulnerabilities.pdf
>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
I'd like to test this series, but before I do that, I'll wait a bit
longer for other review feedback. Please ping me, should I forget.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers
2018-09-20 6:40 [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Hao Wu
` (5 preceding siblings ...)
2018-09-20 13:22 ` [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers Laszlo Ersek
@ 2018-09-20 13:59 ` Kinney, Michael D
2018-09-21 2:14 ` Wu, Hao A
6 siblings, 1 reply; 13+ messages in thread
From: Kinney, Michael D @ 2018-09-20 13:59 UTC (permalink / raw)
To: Wu, Hao A, edk2-devel@lists.01.org, Kinney, Michael D
Cc: Ard Biesheuvel, Laszlo Ersek, Yao, Jiewen, Gao, Liming,
Zeng, Star, Dong, Eric
Hao Wu,
I see that implementations of this API are only
provided for IA32 and X64. Should this be an IA32/X64
specific API in BaseLib? Also, since the API is providing
a C callable function to execute a specific IA32/X64
instruction, should the API be prefixed with Asm to
match the convention of other APIs in BaseLib?
Thanks,
Mike
> -----Original Message-----
> From: Wu, Hao A
> Sent: Wednesday, September 19, 2018 11:41 PM
> To: edk2-devel@lists.01.org
> Cc: Wu, Hao A <hao.a.wu@intel.com>; Ard Biesheuvel
> <ard.biesheuvel@linaro.org>; Laszlo Ersek
> <lersek@redhat.com>; Yao, Jiewen
> <jiewen.yao@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Gao, Liming
> <liming.gao@intel.com>; Zeng, Star
> <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>
> Subject: [PATCH v1 0/5] [CVE-2017-5753] Bounds Check
> Bypass issue in SMI handlers
>
> The series aims to mitigate the Bounds Check Bypass
> (CVE-2017-5753) issues
> within SMI handlers.
>
> A more detailed explanation of the purpose of the
> series is under the
> 'Bounds check bypass mitigation' section of the below
> link:
> https://software.intel.com/security-software-
> guidance/insights/host-firmware-speculative-execution-
> side-channel-mitigation
>
> And the document at:
> https://software.intel.com/security-software-
> guidance/api-app/sites/default/files/337879-analyzing-
> potential-bounds-Check-bypass-vulnerabilities.pdf
>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
>
> Hao Wu (5):
> MdePkg/BaseLib: Add new LoadFence API
> MdeModulePkg/FaultTolerantWrite:[CVE-2017-5753]Fix
> bounds check bypass
> MdeModulePkg/SmmLockBox: [CVE-2017-5753] Fix bounds
> check bypass
> MdeModulePkg/Variable: [CVE-2017-5753] Fix bounds
> check bypass
> UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5753] Fix bounds
> check bypass
>
>
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultToler
> antWriteSmm.c | 2 ++
>
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultToler
> antWriteSmm.inf | 1 +
> MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.c
> | 2 ++
> MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
> | 1 +
>
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.
> c | 3 ++
> MdePkg/Include/Library/BaseLib.h
> | 12 +++++++
> MdePkg/Library/BaseLib/Arm/LoadFence.c
> | 26 ++++++++++++++
> MdePkg/Library/BaseLib/BaseLib.inf
> | 4 +++
> MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> | 15 +++++++-
> MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> | 37 +++++++++++++++++++
> MdePkg/Library/BaseLib/X64/LoadFence.nasm
> | 38 ++++++++++++++++++++
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
> | 1 +
> 12 files changed, 141 insertions(+), 1 deletion(-)
> create mode 100644
> MdePkg/Library/BaseLib/Arm/LoadFence.c
> create mode 100644
> MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> create mode 100644
> MdePkg/Library/BaseLib/X64/LoadFence.nasm
>
> --
> 2.12.0.windows.1
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue in SMI handlers
2018-09-20 13:59 ` Kinney, Michael D
@ 2018-09-21 2:14 ` Wu, Hao A
0 siblings, 0 replies; 13+ messages in thread
From: Wu, Hao A @ 2018-09-21 2:14 UTC (permalink / raw)
To: Kinney, Michael D, edk2-devel@lists.01.org
Cc: Dong, Eric, Gao, Liming, Yao, Jiewen, Laszlo Ersek, Zeng, Star
Hi Mike,
We found that this API needs to be inserted within file:
MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
which is in module:
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
This module (INF file) is consumed by the AARCH64/ARM architectures as
well. That is the reason I do not make this API as IA32/X64 specific.
Best Regards,
Hao Wu
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Kinney, Michael D
> Sent: Thursday, September 20, 2018 9:59 PM
> To: Wu, Hao A; edk2-devel@lists.01.org; Kinney, Michael D
> Cc: Dong, Eric; Gao, Liming; Yao, Jiewen; Laszlo Ersek; Zeng, Star
> Subject: Re: [edk2] [PATCH v1 0/5] [CVE-2017-5753] Bounds Check Bypass issue
> in SMI handlers
>
> Hao Wu,
>
> I see that implementations of this API are only
> provided for IA32 and X64. Should this be an IA32/X64
> specific API in BaseLib? Also, since the API is providing
> a C callable function to execute a specific IA32/X64
> instruction, should the API be prefixed with Asm to
> match the convention of other APIs in BaseLib?
>
> Thanks,
>
> Mike
>
> > -----Original Message-----
> > From: Wu, Hao A
> > Sent: Wednesday, September 19, 2018 11:41 PM
> > To: edk2-devel@lists.01.org
> > Cc: Wu, Hao A <hao.a.wu@intel.com>; Ard Biesheuvel
> > <ard.biesheuvel@linaro.org>; Laszlo Ersek
> > <lersek@redhat.com>; Yao, Jiewen
> > <jiewen.yao@intel.com>; Kinney, Michael D
> > <michael.d.kinney@intel.com>; Gao, Liming
> > <liming.gao@intel.com>; Zeng, Star
> > <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>
> > Subject: [PATCH v1 0/5] [CVE-2017-5753] Bounds Check
> > Bypass issue in SMI handlers
> >
> > The series aims to mitigate the Bounds Check Bypass
> > (CVE-2017-5753) issues
> > within SMI handlers.
> >
> > A more detailed explanation of the purpose of the
> > series is under the
> > 'Bounds check bypass mitigation' section of the below
> > link:
> > https://software.intel.com/security-software-
> > guidance/insights/host-firmware-speculative-execution-
> > side-channel-mitigation
> >
> > And the document at:
> > https://software.intel.com/security-software-
> > guidance/api-app/sites/default/files/337879-analyzing-
> > potential-bounds-Check-bypass-vulnerabilities.pdf
> >
> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Cc: Star Zeng <star.zeng@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> >
> > Hao Wu (5):
> > MdePkg/BaseLib: Add new LoadFence API
> > MdeModulePkg/FaultTolerantWrite:[CVE-2017-5753]Fix
> > bounds check bypass
> > MdeModulePkg/SmmLockBox: [CVE-2017-5753] Fix bounds
> > check bypass
> > MdeModulePkg/Variable: [CVE-2017-5753] Fix bounds
> > check bypass
> > UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5753] Fix bounds
> > check bypass
> >
> >
> > MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultToler
> > antWriteSmm.c | 2 ++
> >
> > MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultToler
> > antWriteSmm.inf | 1 +
> > MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.c
> > | 2 ++
> > MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
> > | 1 +
> >
> > MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.
> > c | 3 ++
> > MdePkg/Include/Library/BaseLib.h
> > | 12 +++++++
> > MdePkg/Library/BaseLib/Arm/LoadFence.c
> > | 26 ++++++++++++++
> > MdePkg/Library/BaseLib/BaseLib.inf
> > | 4 +++
> > MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c
> > | 15 +++++++-
> > MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > | 37 +++++++++++++++++++
> > MdePkg/Library/BaseLib/X64/LoadFence.nasm
> > | 38 ++++++++++++++++++++
> > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
> > | 1 +
> > 12 files changed, 141 insertions(+), 1 deletion(-)
> > create mode 100644
> > MdePkg/Library/BaseLib/Arm/LoadFence.c
> > create mode 100644
> > MdePkg/Library/BaseLib/Ia32/LoadFence.nasm
> > create mode 100644
> > MdePkg/Library/BaseLib/X64/LoadFence.nasm
> >
> > --
> > 2.12.0.windows.1
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 13+ messages in thread