From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 97ABA21A07A92 for ; Tue, 9 Oct 2018 04:24:38 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Oct 2018 04:24:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,360,1534834800"; d="scan'208";a="76577159" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga007.fm.intel.com with ESMTP; 09 Oct 2018 04:23:22 -0700 Received: from fmsmsx158.amr.corp.intel.com (10.18.116.75) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 9 Oct 2018 04:23:21 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx158.amr.corp.intel.com (10.18.116.75) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 9 Oct 2018 04:23:22 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.48]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.245]) with mapi id 14.03.0319.002; Tue, 9 Oct 2018 19:23:16 +0800 From: "Wu, Hao A" To: Jeff Brasen , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Allow additional SDHCI versions Thread-Index: AQHUXM7KB2h1QOw9cEqQC/QWIFs4CKUWbKHg Date: Tue, 9 Oct 2018 11:23:15 +0000 Message-ID: References: <09d9d3505f508b5d565ac909d50efe3d056b85f6.1538757814.git.jbrasen@nvidia.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Allow additional SDHCI versions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Oct 2018 11:24:38 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Je= ff > Brasen > Sent: Saturday, October 06, 2018 1:13 AM > To: edk2-devel@lists.01.org > Cc: Jeff Brasen > Subject: [edk2] [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Allow additional > SDHCI versions >=20 > Clock control is similar in SDHCI versions greater then version 3. Add > support for more recent versions of the controller specification. >=20 > SD card support for 1.8V is also present in controller versions 3 and > greater. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jeff Brasen Hi, Some minor comments: A. I suggest to list a supported controller spec. versions range like: if (((ControllerVer & 0xFF) >=3D SD_MMC_HC_CTRL_VER_300) && ((ControllerVer & 0xFF) <=3D SD_MMC_HC_CTRL_VER_420)) { to restrict the supported spec. versions for the driver. B. I have submitted a Bugzilla tracker for your proposed series: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1233 =20 Could you help to include this information in the commit messages of your proposed patches? Best Regards, Hao Wu > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 2 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c > index d3f77ed..12b4659 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c > @@ -978,7 +978,7 @@ SdCardIdentification ( > return Status; > } >=20 > - if ((ControllerVer & 0xFF) =3D=3D SD_MMC_HC_CTRL_VER_300) { > + if ((ControllerVer & 0xFF) >=3D SD_MMC_HC_CTRL_VER_300) { > S18r =3D TRUE; > } else if (((ControllerVer & 0xFF) =3D=3D SD_MMC_HC_CTRL_VER_100) || > ((ControllerVer & 0xFF) =3D=3D SD_MMC_HC_CTRL_VER_200)) { > S18r =3D FALSE; > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index 3b9a184..de282bf 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -782,7 +782,7 @@ SdMmcHcClockSupply ( > // > // Set SDCLK Frequency Select and Internal Clock Enable fields in Cloc= k > Control register. > // > - if ((ControllerVer & 0xFF) =3D=3D SD_MMC_HC_CTRL_VER_300) { > + if ((ControllerVer & 0xFF) >=3D SD_MMC_HC_CTRL_VER_300) { > ASSERT (Divisor <=3D 0x3FF); > ClockCtrl =3D ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2); > } else if (((ControllerVer & 0xFF) =3D=3D 0) || ((ControllerVer & 0xFF= ) =3D=3D 1)) { > -- > 2.7.4 >=20 >=20 > -------------------------------------------------------------------------= ---------- > This email message is for the sole use of the intended recipient(s) and m= ay > contain > confidential information. Any unauthorized review, use, disclosure or > distribution > is prohibited. If you are not the intended recipient, please contact the= sender > by > reply email and destroy all copies of the original message. > -------------------------------------------------------------------------= ---------- > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel