From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 826552116747F for ; Thu, 11 Oct 2018 22:25:17 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2018 22:25:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,371,1534834800"; d="scan'208";a="77447490" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga007.fm.intel.com with ESMTP; 11 Oct 2018 22:24:34 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 11 Oct 2018 22:24:33 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.48]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.245]) with mapi id 14.03.0319.002; Fri, 12 Oct 2018 13:24:31 +0800 From: "Wu, Hao A" To: Marcin Wojtas , "edk2-devel@lists.01.org" CC: "Tian, Feng" , "Kinney, Michael D" , "Gao, Liming" , "leif.lindholm@linaro.org" , "ard.biesheuvel@linaro.org" , "nadavh@marvell.com" , "jsd@semihalf.com" , "tm@semihalf.com" Thread-Topic: [PATCH v2 0/4] SdMmcOverride extension Thread-Index: AQHUXK7ncodTjw60Y0WMq/dguBS85KUbG6PQ Date: Fri, 12 Oct 2018 05:24:31 +0000 Message-ID: References: <1538745911-22484-1-git-send-email-mw@semihalf.com> In-Reply-To: <1538745911-22484-1-git-send-email-mw@semihalf.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 0/4] SdMmcOverride extension X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 05:25:17 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Marcin, Please grant me some time for this series. Since I found that the extension of the SdMmc override protocol (mainly the 3rd and 4th patch of the series) may have something overlaps with a (internal) request to configure the driver strength parameter and operating clock frequency of the SD/EMMC devices. For the (driver strength/operating freq) customize, we already have a proposal on the way. So I am wondering if you could grant me some time to investigate whether both the cases can be addressed together based on your proposed patch. Thanks in advance. Best Regards, Hao Wu > -----Original Message----- > From: Marcin Wojtas [mailto:mw@semihalf.com] > Sent: Friday, October 05, 2018 9:25 PM > To: edk2-devel@lists.01.org > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org;= Wu, > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com; > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com > Subject: [PATCH v2 0/4] SdMmcOverride extension >=20 > Hi, >=20 > This is the second version of the patchset. Initial one was > interleaved with the fixes, which after split got already merged. > The biggest change is - resigning from the new callbacks > and extending parameter lists of both NotifyPhase and Capability > routines. >=20 > Patches are available in the github: > https://github.com/MarvellEmbeddedProcessors/edk2-open- > platform/commits/sdmmc-override-upstream-r20181005 >=20 > Please note that extending SdMmcOverride protocol was impacting > so far the only user of it (Synquacer controller). In paralel > edk2-platforms patchset, a patch can be found: > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride") > which immunizes for above and future extensions of the protocol: > https://github.com/MarvellEmbeddedProcessors/edk2-open- > platform/commits/xenon-upstream-r20181005 >=20 > I'm looking forward to the comments and remarks. >=20 > Best regards, > Marcin >=20 > Changelog: > v1 -> v2 > * Rebase onto newest master > * 1/4 [new patch] - preparation for extending NotifyPhase > * 2/4 - UhsSignaling as a part of NotifyPhase > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase > * 4/4 - Allow updating BaseClkFreq via Capability instead of the > independent callback. >=20 > Marcin Wojtas (2): > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in > NotifyPhase > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency >=20 > Tomasz Michalec (2): > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride > protocol > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to > SdMmcOverride >=20 > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 + > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++- > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215 > ++++++++++++++------ > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108 ++++++++- > - > 7 files changed, 383 insertions(+), 95 deletions(-) >=20 > -- > 2.7.4