From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A9A522116745C for ; Fri, 26 Oct 2018 00:33:12 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Oct 2018 00:33:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,427,1534834800"; d="scan'208";a="98861060" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga002.fm.intel.com with ESMTP; 26 Oct 2018 00:33:10 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 26 Oct 2018 00:33:08 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 26 Oct 2018 00:33:08 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.117]) by shsmsx102.ccr.corp.intel.com ([169.254.2.84]) with mapi id 14.03.0415.000; Fri, 26 Oct 2018 15:33:06 +0800 From: "Wu, Hao A" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , "Wang, Jian J" , "Yao, Jiewen" Thread-Topic: [PATCH V2 1/4] MdeModulePkg XhciDxe: Extract new XhciInsertAsyncIntTransfer function Thread-Index: AQHUbO6xHdI+4/nm+0yY6EfVuKIdDKUxIVVw Date: Fri, 26 Oct 2018 07:33:05 +0000 Message-ID: References: <1540532541-115032-1-git-send-email-star.zeng@intel.com> <1540532541-115032-2-git-send-email-star.zeng@intel.com> In-Reply-To: <1540532541-115032-2-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH V2 1/4] MdeModulePkg XhciDxe: Extract new XhciInsertAsyncIntTransfer function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Oct 2018 07:33:12 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Star, The interface for function XhciInsertAsyncIntTransfer() does not match betw= een XhciSched.c and XhciSched.h. Other than that: Reviewed-by: Hao Wu Best Regards, Hao Wu > -----Original Message----- > From: Zeng, Star > Sent: Friday, October 26, 2018 1:42 PM > To: edk2-devel@lists.01.org > Cc: Zeng, Star; Ni, Ruiyu; Wu, Hao A; Wang, Jian J; Yao, Jiewen > Subject: [PATCH V2 1/4] MdeModulePkg XhciDxe: Extract new > XhciInsertAsyncIntTransfer function >=20 > V2: > Add the missing "FreePool (Data);". > Remove the unnecessary indentation change. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1274 >=20 > Extract new XhciInsertAsyncIntTransfer function from > XhcAsyncInterruptTransfer. >=20 > It is code preparation for following patch, > no essential functional change. >=20 > Cc: Ruiyu Ni > Cc: Hao Wu > Cc: Jian J Wang > Cc: Jiewen Yao > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 18 +-------- > MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 65 > ++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h | 28 ++++++++++++++ > 3 files changed, 94 insertions(+), 17 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > index f1c60bef01c0..7f64f9c7c982 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > @@ -1346,7 +1346,6 @@ XhcAsyncInterruptTransfer ( > EFI_STATUS Status; > UINT8 SlotId; > UINT8 Index; > - UINT8 *Data; > EFI_TPL OldTpl; >=20 > // > @@ -1413,36 +1412,21 @@ XhcAsyncInterruptTransfer ( > goto ON_EXIT; > } >=20 > - Data =3D AllocateZeroPool (DataLength); > - > - if (Data =3D=3D NULL) { > - DEBUG ((EFI_D_ERROR, "XhcAsyncInterruptTransfer: failed to allocate > buffer\n")); > - Status =3D EFI_OUT_OF_RESOURCES; > - goto ON_EXIT; > - } > - > - Urb =3D XhcCreateUrb ( > + Urb =3D XhciInsertAsyncIntTransfer ( > Xhc, > DeviceAddress, > EndPointAddress, > DeviceSpeed, > MaximumPacketLength, > - XHC_INT_TRANSFER_ASYNC, > - NULL, > - Data, > DataLength, > CallBackFunction, > Context > ); > - > if (Urb =3D=3D NULL) { > - DEBUG ((EFI_D_ERROR, "XhcAsyncInterruptTransfer: failed to create > URB\n")); > - FreePool (Data); > Status =3D EFI_OUT_OF_RESOURCES; > goto ON_EXIT; > } >=20 > - InsertHeadList (&Xhc->AsyncIntTransfers, &Urb->UrbList); > // > // Ring the doorbell > // > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > index 166c44bf5e66..75959ae08363 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > @@ -1411,6 +1411,71 @@ XhciDelAllAsyncIntTransfers ( > } >=20 > /** > + Insert a single asynchronous interrupt transfer for > + the device and endpoint. > + > + @param Xhc The XHCI Instance > + @param BusAddr The logical device address assigned by UsbBus dr= iver > + @param EpAddr Endpoint addrress > + @param DevSpeed The device speed > + @param MaxPacket The max packet length of the endpoint > + @param DataLen The length of data buffer > + @param Callback The function to call when data is transferred > + @param Context The context to the callback > + > + @return Created URB or NULL > + > +**/ > +URB * > +XhciInsertAsyncIntTransfer ( > + IN USB_XHCI_INSTANCE *Xhc, > + IN UINT8 BusAddr, > + IN UINT8 EpAddr, > + IN UINT8 DevSpeed, > + IN UINTN MaxPacket, > + IN UINTN DataLen, > + IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback, > + IN VOID *Context > + ) > +{ > + VOID *Data; > + URB *Urb; > + > + Data =3D AllocateZeroPool (DataLen); > + if (Data =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "%a: failed to allocate buffer\n", > __FUNCTION__)); > + return NULL; > + } > + > + Urb =3D XhcCreateUrb ( > + Xhc, > + BusAddr, > + EpAddr, > + DevSpeed, > + MaxPacket, > + XHC_INT_TRANSFER_ASYNC, > + NULL, > + Data, > + DataLen, > + Callback, > + Context > + ); > + if (Urb =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "%a: failed to create URB\n", __FUNCTION__)); > + FreePool (Data); > + return NULL; > + } > + > + // > + // New asynchronous transfer must inserted to the head. > + // Check the comments in XhcMoniteAsyncRequests > + // > + InsertHeadList (&Xhc->AsyncIntTransfers, &Urb->UrbList); > + > + return Urb; > +} > + > +/** > Update the queue head for next round of asynchronous transfer >=20 > @param Xhc The XHCI Instance. > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h > index 097408828a1f..cd1403f2842a 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h > @@ -853,6 +853,34 @@ XhciDelAllAsyncIntTransfers ( > ); >=20 > /** > + Insert a single asynchronous interrupt transfer for > + the device and endpoint. > + > + @param Xhc The XHCI Instance > + @param BusAddr The logical device address assigned by UsbBus dr= iver > + @param EpAddr Endpoint addrress > + @param DevSpeed The device speed > + @param MaxPacket The max packet length of the endpoint > + @param DataLen The length of data buffer > + @param Callback The function to call when data is transferred > + @param Context The context to the callback > + > + @return Created URB or NULL > + > +**/ > +URB * > +XhciInsertAsyncIntTransfer ( > + IN USB_XHCI_INSTANCE *Xhc, > + IN UINT8 DeviceAddress, > + IN UINT8 EndPointAddress, > + IN UINT8 DeviceSpeed, > + IN UINTN MaximumPacketLength, > + IN UINTN DataLength, > + IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction, > + IN VOID *Context > + ); > + > +/** > Set Bios Ownership >=20 > @param Xhc The XHCI Instance. > -- > 2.7.0.windows.1