From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B9E692117B577 for ; Thu, 1 Nov 2018 00:11:26 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2018 00:11:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,451,1534834800"; d="scan'208";a="105041199" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 01 Nov 2018 00:11:25 -0700 Received: from fmsmsx120.amr.corp.intel.com (10.18.124.208) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 1 Nov 2018 00:11:25 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx120.amr.corp.intel.com (10.18.124.208) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 1 Nov 2018 00:11:25 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.117]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.102]) with mapi id 14.03.0415.000; Thu, 1 Nov 2018 15:11:23 +0800 From: "Wu, Hao A" To: 'Marcin Wojtas' , Ard Biesheuvel , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" , "Gao, Liming" , "leif.lindholm@linaro.org" , "ard.biesheuvel@linaro.org" , "nadavh@marvell.com" , "jsd@semihalf.com" , "tm@semihalf.com" Thread-Topic: [PATCH v2 0/4] SdMmcOverride extension Thread-Index: AQHUXK7ncodTjw60Y0WMq/dguBS85KU3Q28g Date: Thu, 1 Nov 2018 07:11:23 +0000 Message-ID: References: <1538745911-22484-1-git-send-email-mw@semihalf.com> In-Reply-To: <1538745911-22484-1-git-send-email-mw@semihalf.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 0/4] SdMmcOverride extension X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Nov 2018 07:11:26 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Marcin and Ard, > -----Original Message----- > From: Marcin Wojtas [mailto:mw@semihalf.com] > Sent: Friday, October 05, 2018 9:25 PM > To: edk2-devel@lists.01.org > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org;= Wu, > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com; > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com > Subject: [PATCH v2 0/4] SdMmcOverride extension >=20 > Hi, >=20 > This is the second version of the patchset. Initial one was > interleaved with the fixes, which after split got already merged. > The biggest change is - resigning from the new callbacks > and extending parameter lists of both NotifyPhase and Capability > routines. >=20 > Patches are available in the github: > https://github.com/MarvellEmbeddedProcessors/edk2-open- > platform/commits/sdmmc-override-upstream-r20181005 >=20 > Please note that extending SdMmcOverride protocol was impacting > so far the only user of it (Synquacer controller). In paralel > edk2-platforms patchset, a patch can be found: > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride") > which immunizes for above and future extensions of the protocol: > https://github.com/MarvellEmbeddedProcessors/edk2-open- > platform/commits/xenon-upstream-r20181005 >=20 > I'm looking forward to the comments and remarks. Since there are protocol service interface changes, maybe a version change (macro EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION) for the SdMmc Override Proto= col is needed. Please share your thoughts on this one. Thanks. Best Regards, Hao Wu >=20 > Best regards, > Marcin >=20 > Changelog: > v1 -> v2 > * Rebase onto newest master > * 1/4 [new patch] - preparation for extending NotifyPhase > * 2/4 - UhsSignaling as a part of NotifyPhase > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase > * 4/4 - Allow updating BaseClkFreq via Capability instead of the > independent callback. >=20 > Marcin Wojtas (2): > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in > NotifyPhase > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency >=20 > Tomasz Michalec (2): > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride > protocol > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to > SdMmcOverride >=20 > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 + > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++- > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215 > ++++++++++++++------ > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108 ++++++++- > - > 7 files changed, 383 insertions(+), 95 deletions(-) >=20 > -- > 2.7.4