From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 725C32118F783 for ; Mon, 12 Nov 2018 23:38:50 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Nov 2018 23:38:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,498,1534834800"; d="scan'208";a="99804858" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 12 Nov 2018 23:38:49 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 12 Nov 2018 23:38:48 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.117]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.214]) with mapi id 14.03.0415.000; Tue, 13 Nov 2018 15:38:46 +0800 From: "Wu, Hao A" To: Marcin Wojtas , "edk2-devel@lists.01.org" CC: "leif.lindholm@linaro.org" , "Kinney, Michael D" , "Gao, Liming" , "ard.biesheuvel@linaro.org" , "nadavh@marvell.com" , "jsd@semihalf.com" , "tm@semihalf.com" , "jaz@semihalf.com" Thread-Topic: [PATCH v4 0/4] SdMmcOverride extension Thread-Index: AQHUeIA5kfp7UYcL5EGoIqVttOtJJaVNVQ5w Date: Tue, 13 Nov 2018 07:38:46 +0000 Message-ID: References: <1541804487-27458-1-git-send-email-mw@semihalf.com> In-Reply-To: <1541804487-27458-1-git-send-email-mw@semihalf.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v4 0/4] SdMmcOverride extension X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Nov 2018 07:38:50 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Marcin, The code changes look good to me. Could you please grant me some time for some additional tests for these patches? I will inform you with the results sometime next week. Thanks in advance. Best Regards, Hao Wu > -----Original Message----- > From: Marcin Wojtas [mailto:mw@semihalf.com] > Sent: Saturday, November 10, 2018 7:01 AM > To: edk2-devel@lists.01.org > Cc: leif.lindholm@linaro.org; Wu, Hao A; Kinney, Michael D; Gao, Liming; > ard.biesheuvel@linaro.org; nadavh@marvell.com; mw@semihalf.com; > jsd@semihalf.com; tm@semihalf.com; jaz@semihalf.com > Subject: [PATCH v4 0/4] SdMmcOverride extension >=20 > Hi, >=20 > Although I could've waited for Hao's remarks, I think it may > be better if he takes a look at much cleaner code, which > addresses v3 review comments. > The newest version of the patchset cleans-up significantly > patches 2&3 by removing code duplication and other minor > improvements. >=20 > Patches are available in the github: > https://github.com/MarvellEmbeddedProcessors/edk2-open- > platform/commits/sdmmc-override-upstream-r20181109 >=20 > Please note that extending SdMmcOverride protocol was impacting > so far the only user of it (Synquacer controller). In paralel > edk2-platforms patchset, a patch can be found: > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride") > which adjust to the new API. > https://github.com/MarvellEmbeddedProcessors/edk2-open- > platform/commits/xenon-upstream-r20181109 >=20 > I'm looking forward to the comments and remarks. >=20 > Best regards, > Marcin >=20 > Changelog: > v3->v4 > * 2/4: > - avoid duplication by calling SdMmcOverride callback in > SdMmcHcUhsSignaling >=20 > * 3/4: > - avoid duplication by calling SdMmcOverride callback in > EmmcSwitchClockFreq >=20 > * 4/4: > - add Ard's RB >=20 > v2->v3 > * 1/4: > - rename new parameter to PhaseData > - add Ard's RB >=20 > * 2/4: > - s/Controler/Controller/ > - remove all references to MMC_SDR_50 mode > - rename and reorder MMC bus modes > - rename enum: s/SD_MMC_UHS_TIMING/SD_MMC_BUS_MODE/ > and move it to protocol header in order to drop including private one > - fix if condition in EmmcSwitchToHighSpeed > - call SdMmcHcUhsSignaling unconditionally before SdMmcOverride > callback, so that protocol producer can optionally modify only quirky > timing mode values. >=20 > *4/4 > - bump protocol version to 2 > - remove redundant assert from SdMmcPciHcDriverBindingStart > (BaseClkFreq is already checked in SdMmcHcInitClockFreq) > - update comment in SdMmcHcInitClockFreq > - restore original DumpCapabilityReg and append >=20 > v1 -> v2 > * Rebase onto newest master > * 1/4 [new patch] - preparation for extending NotifyPhase > * 2/4 - UhsSignaling as a part of NotifyPhase > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase > * 4/4 - Allow updating BaseClkFreq via Capability instead of the > independent callback. >=20 >=20 > Marcin Wojtas (2): > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency >=20 > Tomasz Michalec (2): > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride > protocol > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to > SdMmcOverride >=20 > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 + > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 42 ++++++- > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 29 ++++- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 121 ++++++++++- > -------- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 35 ++++-- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 13 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 124 > +++++++++++++++++--- > 7 files changed, 280 insertions(+), 90 deletions(-) >=20 > -- > 2.7.4