From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8E99921962301 for ; Fri, 16 Nov 2018 00:26:49 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Nov 2018 00:26:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,239,1539673200"; d="scan'208";a="106770644" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga004.fm.intel.com with ESMTP; 16 Nov 2018 00:26:48 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 16 Nov 2018 00:26:48 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.117]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.199]) with mapi id 14.03.0415.000; Fri, 16 Nov 2018 16:26:46 +0800 From: "Wu, Hao A" To: Ashish Singhal , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Add V4 64bit ADMA2 support. Thread-Index: AQHUd5UTf7Y6QTY22U64UplUJ6OB4aVSDU9Q Date: Fri, 16 Nov 2018 08:26:45 +0000 Message-ID: References: <4d91387d2b96ec0b20b2aa78aaacc921ae258d0f.1541703096.git.ashishsingha@nvidia.com> <389f4c6aa77dc85f23d70a524f2fda4e4212a74a.1541703096.git.ashishsingha@nvidia.com> In-Reply-To: <389f4c6aa77dc85f23d70a524f2fda4e4212a74a.1541703096.git.ashishsingha@nvidia.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Add V4 64bit ADMA2 support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Nov 2018 08:26:49 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Ashish Singhal > Sent: Friday, November 09, 2018 2:58 AM > To: edk2-devel@lists.01.org > Cc: Ashish Singhal > Subject: [edk2] [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Add V4 64bit > ADMA2 support. >=20 > If V4 64 bit address mode is enabled in compatibility register, > program controller to enable V4 host mode and use appropriate > ADMA descriptors supporting 64 bit addresses. Hi, I have a quick check on the SD Host Controller Simplified Specification Ver= sion 4.20. When the 'Host Version 4 Enable' bit in the HC2 Register is set, for = host controller with version newer than 3.0: SDMA mode transfer no longer use SDMA System Address Register for system address, and this SDMA System Address Register will be used as 32-bit Block Count instead under certain case. So I think the way to start an SDMA mode transfer is not the same between h= ost controllers with different versions. However, I do not see this patch handl= e this potential behavior change. Please correct me if my understanding is incorrect here. Also, could you help to provide information on what tests have been perform= ed on this series? Thanks in advance. Best Regards, Hao Wu >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ashish Singhal > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 4 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 183 > +++++++++++++++++---- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 28 +++- > 3 files changed, 183 insertions(+), 32 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > index c683600..22795df 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > @@ -2,6 +2,7 @@ >=20 > Provides some data structure definitions used by the SD/MMC host contr= oller > driver. >=20 > +Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. > Copyright (c) 2015, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the BS= D > License > @@ -144,7 +145,8 @@ typedef struct { > BOOLEAN Started; > UINT64 Timeout; >=20 > - SD_MMC_HC_ADMA_DESC_LINE *AdmaDesc; > + SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc; > + SD_MMC_HC_ADMA_64_DESC_LINE *Adma64Desc; > EFI_PHYSICAL_ADDRESS AdmaDescPhy; > VOID *AdmaMap; > UINT32 AdmaPages; > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index e506875..bcd2707 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -4,6 +4,7 @@ >=20 > It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. >=20 > + Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. > Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > @@ -418,6 +419,36 @@ SdMmcHcWaitMmioSet ( > } >=20 > /** > + Get the controller version information from the specified slot. > + > + @param[in] PciIo The PCI IO protocol instance. > + @param[in] Slot The slot number of the SD card to send the > command to. > + @param[out] Version The buffer to store the version informatio= n. > + > + @retval EFI_SUCCESS The operation executes successfully. > + @retval Others The operation fails. > + > +**/ > +EFI_STATUS > +SdMmcHcGetControllerVersion ( > + IN EFI_PCI_IO_PROTOCOL *PciIo, > + IN UINT8 Slot, > + OUT UINT16 *Version > + ) > +{ > + EFI_STATUS Status; > + > + Status =3D SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, > sizeof (UINT16), Version); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + *Version &=3D 0xFF; > + > + return EFI_SUCCESS; > +} > + > +/** > Software reset the specified SD/MMC host controller and enable all > interrupts. >=20 > @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA > instance. > @@ -776,18 +807,18 @@ SdMmcHcClockSupply ( >=20 > DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", > BaseClkFreq, Divisor, ClockFreq)); >=20 > - Status =3D SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, > sizeof (ControllerVer), &ControllerVer); > + Status =3D SdMmcHcGetControllerVersion (PciIo, Slot, &ControllerVer); > if (EFI_ERROR (Status)) { > return Status; > } > // > // Set SDCLK Frequency Select and Internal Clock Enable fields in Cloc= k > Control register. > // > - if (((ControllerVer & 0xFF) >=3D SD_MMC_HC_CTRL_VER_300) && > - ((ControllerVer & 0xFF) <=3D SD_MMC_HC_CTRL_VER_420)) { > + if ((ControllerVer >=3D SD_MMC_HC_CTRL_VER_300) && > + (ControllerVer <=3D SD_MMC_HC_CTRL_VER_420)) { > ASSERT (Divisor <=3D 0x3FF); > ClockCtrl =3D ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2); > - } else if (((ControllerVer & 0xFF) =3D=3D 0) || ((ControllerVer & 0xFF= ) =3D=3D 1)) { > + } else if ((ControllerVer =3D=3D 0) || (ControllerVer =3D=3D 1)) { > // > // Only the most significant bit can be used as divisor. > // > @@ -935,6 +966,41 @@ SdMmcHcSetBusWidth ( > } >=20 > /** > + Configure V4 64 bit system address support at initialization. > + > + @param[in] PciIo The PCI IO protocol instance. > + @param[in] Slot The slot number of the SD card to send the c= ommand > to. > + @param[in] Capability The capability of the slot. > + > + @retval EFI_SUCCESS The clock is supplied successfully. > + > +**/ > +EFI_STATUS > +SdMmcHcV4Init64BitSupport ( > + IN EFI_PCI_IO_PROTOCOL *PciIo, > + IN UINT8 Slot, > + IN SD_MMC_HC_SLOT_CAP Capability > + ) > +{ > + EFI_STATUS Status; > + UINT16 HostCtrl2; > + > + // > + // Check if V4 64bit support is available > + // > + if (Capability.SysBus64V4 =3D=3D TRUE) { > + HostCtrl2 =3D SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN; > + Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof > (HostCtrl2), &HostCtrl2); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n")); > + } > + > + return EFI_SUCCESS; > +} > + > +/** > Supply SD/MMC card with lowest clock frequency at initialization. >=20 > @param[in] PciIo The PCI IO protocol instance. > @@ -1101,6 +1167,11 @@ SdMmcHcInitHost ( > PciIo =3D Private->PciIo; > Capability =3D Private->Capability[Slot]; >=20 > + Status =3D SdMmcHcV4Init64BitSupport (PciIo, Slot, Capability); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > Status =3D SdMmcHcInitClockFreq (PciIo, Slot, Capability); > if (EFI_ERROR (Status)) { > return Status; > @@ -1169,7 +1240,7 @@ SdMmcHcLedOnOff ( > /** > Build ADMA descriptor table for transfer. >=20 > - Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for detai= ls. > + Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for detai= ls. >=20 > @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. >=20 > @@ -1187,49 +1258,69 @@ BuildAdmaDescTable ( > UINT64 Entries; > UINT32 Index; > UINT64 Remaining; > - UINT32 Address; > + UINT64 Address; > UINTN TableSize; > EFI_PCI_IO_PROTOCOL *PciIo; > EFI_STATUS Status; > UINTN Bytes; > + UINT16 ControllerVer; > + BOOLEAN AddressingMode64 =3D FALSE; > + UINTN DescSize =3D sizeof (SD_MMC_HC_ADMA_32_DESC_= LINE); > + VOID *AdmaDesc =3D NULL; >=20 > Data =3D Trb->DataPhy; > DataLen =3D Trb->DataLen; > PciIo =3D Trb->Private->PciIo; > + > // > - // Only support 32bit ADMA Descriptor Table > + // Detect whether 64bit addressing is supported. > // > - if ((Data >=3D 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) { > + Status =3D SdMmcHcGetControllerVersion (PciIo, Trb->Slot, &ControllerV= er); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_400) { > + Status =3D SdMmcHcCheckMmioSet(PciIo, Trb->Slot, > SD_MMC_HC_HOST_CTRL2, 0x2, > + SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, > SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN); > + if (!EFI_ERROR (Status)) { > + AddressingMode64 =3D TRUE; > + DescSize =3D sizeof (SD_MMC_HC_ADMA_64_DESC_LINE); > + } > + } > + // > + // Check for valid ranges in 32bit ADMA Descriptor Table > + // > + if (AddressingMode64 =3D=3D FALSE && > + ((Data >=3D 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)))= { > return EFI_INVALID_PARAMETER; > } > // > // Address field shall be set on 32-bit boundary (Lower 2-bit is alway= s set to 0) > - // for 32-bit address descriptor table. > // > if ((Data & (BIT0 | BIT1)) !=3D 0) { > DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not > aligned to 4 bytes boundary!\n", Data)); > } >=20 > Entries =3D DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), > ADMA_MAX_DATA_PER_LINE); > - TableSize =3D (UINTN)MultU64x32 (Entries, sizeof > (SD_MMC_HC_ADMA_DESC_LINE)); > + TableSize =3D (UINTN)MultU64x32 (Entries, DescSize); > Trb->AdmaPages =3D (UINT32)EFI_SIZE_TO_PAGES (TableSize); > Status =3D PciIo->AllocateBuffer ( > PciIo, > AllocateAnyPages, > EfiBootServicesData, > EFI_SIZE_TO_PAGES (TableSize), > - (VOID **)&Trb->AdmaDesc, > + (VOID **)&AdmaDesc, > 0 > ); > if (EFI_ERROR (Status)) { > return EFI_OUT_OF_RESOURCES; > } > - ZeroMem (Trb->AdmaDesc, TableSize); > + ZeroMem (AdmaDesc, TableSize); > Bytes =3D TableSize; > Status =3D PciIo->Map ( > PciIo, > EfiPciIoOperationBusMasterCommonBuffer, > - Trb->AdmaDesc, > + AdmaDesc, > &Bytes, > &Trb->AdmaDescPhy, > &Trb->AdmaMap > @@ -1242,12 +1333,13 @@ BuildAdmaDescTable ( > PciIo->FreeBuffer ( > PciIo, > EFI_SIZE_TO_PAGES (TableSize), > - Trb->AdmaDesc > + AdmaDesc > ); > return EFI_OUT_OF_RESOURCES; > } >=20 > - if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) { > + if ((AddressingMode64 =3D=3D FALSE) && > + (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) { > // > // The ADMA doesn't support 64bit addressing. > // > @@ -1258,25 +1350,49 @@ BuildAdmaDescTable ( > PciIo->FreeBuffer ( > PciIo, > EFI_SIZE_TO_PAGES (TableSize), > - Trb->AdmaDesc > + AdmaDesc > ); > return EFI_DEVICE_ERROR; > } >=20 > Remaining =3D DataLen; > - Address =3D (UINT32)Data; > + Address =3D Data; > + if (AddressingMode64 =3D=3D FALSE) { > + Trb->Adma32Desc =3D AdmaDesc; > + Trb->Adma64Desc =3D NULL; > + } else { > + Trb->Adma64Desc =3D AdmaDesc; > + Trb->Adma32Desc =3D NULL; > + } > for (Index =3D 0; Index < Entries; Index++) { > - if (Remaining <=3D ADMA_MAX_DATA_PER_LINE) { > - Trb->AdmaDesc[Index].Valid =3D 1; > - Trb->AdmaDesc[Index].Act =3D 2; > - Trb->AdmaDesc[Index].Length =3D (UINT16)Remaining; > - Trb->AdmaDesc[Index].Address =3D Address; > - break; > + if (AddressingMode64 =3D=3D FALSE) { > + if (Remaining < ADMA_MAX_DATA_PER_LINE) { > + Trb->Adma32Desc[Index].Valid =3D 1; > + Trb->Adma32Desc[Index].Act =3D 2; > + Trb->Adma32Desc[Index].Length =3D (UINT16)Remaining; > + Trb->Adma32Desc[Index].Address =3D (UINT32)Address; > + break; > + } else { > + Trb->Adma32Desc[Index].Valid =3D 1; > + Trb->Adma32Desc[Index].Act =3D 2; > + Trb->Adma32Desc[Index].Length =3D 0; > + Trb->Adma32Desc[Index].Address =3D (UINT32)Address; > + } > } else { > - Trb->AdmaDesc[Index].Valid =3D 1; > - Trb->AdmaDesc[Index].Act =3D 2; > - Trb->AdmaDesc[Index].Length =3D 0; > - Trb->AdmaDesc[Index].Address =3D Address; > + if (Remaining < ADMA_MAX_DATA_PER_LINE) { > + Trb->Adma64Desc[Index].Valid =3D 1; > + Trb->Adma64Desc[Index].Act =3D 2; > + Trb->Adma64Desc[Index].Length =3D (UINT16)Remaining; > + Trb->Adma64Desc[Index].LowerAddress =3D (UINT32)(Address & > MAX_UINT32); > + Trb->Adma64Desc[Index].UpperAddress =3D (UINT32)(Address>>32); > + break; > + } else { > + Trb->Adma64Desc[Index].Valid =3D 1; > + Trb->Adma64Desc[Index].Act =3D 2; > + Trb->Adma64Desc[Index].Length =3D 0; > + Trb->Adma64Desc[Index].LowerAddress =3D (UINT32)(Address & > MAX_UINT32); > + Trb->Adma64Desc[Index].UpperAddress =3D (UINT32)(Address>>32); > + } > } >=20 > Remaining -=3D ADMA_MAX_DATA_PER_LINE; > @@ -1286,7 +1402,7 @@ BuildAdmaDescTable ( > // > // Set the last descriptor line as end of descriptor table > // > - Trb->AdmaDesc[Index].End =3D 1; > + AddressingMode64 ? (Trb->Adma64Desc[Index].End =3D 1) : (Trb- > >Adma32Desc[Index].End =3D 1); > return EFI_SUCCESS; > } >=20 > @@ -1430,11 +1546,18 @@ SdMmcFreeTrb ( > Trb->AdmaMap > ); > } > - if (Trb->AdmaDesc !=3D NULL) { > + if (Trb->Adma32Desc !=3D NULL) { > + PciIo->FreeBuffer ( > + PciIo, > + Trb->AdmaPages, > + Trb->Adma32Desc > + ); > + } > + if (Trb->Adma64Desc !=3D NULL) { > PciIo->FreeBuffer ( > PciIo, > Trb->AdmaPages, > - Trb->AdmaDesc > + Trb->Adma64Desc > ); > } > if (Trb->DataMap !=3D NULL) { > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > index cc138fc..a6234f1 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > @@ -2,6 +2,7 @@ >=20 > Provides some data structure definitions used by the SD/MMC host contr= oller > driver. >=20 > +Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. > Copyright (c) 2015, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the BS= D > License > @@ -78,6 +79,9 @@ typedef enum { > // > #define ADMA_MAX_DATA_PER_LINE 0x10000 >=20 > +// > +// ADMA descriptor for 32b addressing. > +// > typedef struct { > UINT32 Valid:1; > UINT32 End:1; > @@ -87,7 +91,23 @@ typedef struct { > UINT32 Reserved1:10; > UINT32 Length:16; > UINT32 Address; > -} SD_MMC_HC_ADMA_DESC_LINE; > +} SD_MMC_HC_ADMA_32_DESC_LINE; > + > +// > +// ADMA descriptor for 64b addressing. > +// > +typedef struct { > + UINT32 Valid:1; > + UINT32 End:1; > + UINT32 Int:1; > + UINT32 Reserved:1; > + UINT32 Act:2; > + UINT32 Reserved1:10; > + UINT32 Length:16; > + UINT32 LowerAddress; > + UINT32 UpperAddress; > + UINT32 Reserved2; > +} SD_MMC_HC_ADMA_64_DESC_LINE; >=20 > #define SD_MMC_SDMA_BOUNDARY 512 * 1024 > #define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1)) > @@ -145,6 +165,12 @@ typedef struct { > #define SD_MMC_HC_CTRL_VER_410 0x04 > #define SD_MMC_HC_CTRL_VER_420 0x05 >=20 > +// > +// SD Host controller V4 Support > +// > +#define SD_MMC_HC_V4_EN BIT12 > +#define SD_MMC_HC_64_ADDR_EN BIT13 > + > /** > Dump the content of SD/MMC host controller's Capability Register. >=20 > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel