From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 340EE2119736D for ; Fri, 30 Nov 2018 00:00:40 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Nov 2018 00:00:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,297,1539673200"; d="scan'208";a="114110056" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga001.jf.intel.com with ESMTP; 30 Nov 2018 00:00:38 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 30 Nov 2018 00:00:38 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.203]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.201]) with mapi id 14.03.0415.000; Fri, 30 Nov 2018 16:00:17 +0800 From: "Wu, Hao A" To: Ashish Singhal , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH v6 1/2] MdeModulePkg/SdMmcPciHcDxe: Declare V4 64 bit address capability Thread-Index: AQHUiBfUTbp/CPZwcEuNf6dcq/4D0aVn42/w Date: Fri, 30 Nov 2018 08:00:17 +0000 Message-ID: References: <813fddd12ccfd0a0958930438d5827c221aeafea.1543515597.git.ashishsingha@nvidia.com> In-Reply-To: <813fddd12ccfd0a0958930438d5827c221aeafea.1543515597.git.ashishsingha@nvidia.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v6 1/2] MdeModulePkg/SdMmcPciHcDxe: Declare V4 64 bit address capability X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Nov 2018 08:00:40 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Ashish Singhal > Sent: Friday, November 30, 2018 3:15 AM > To: edk2-devel@lists.01.org > Cc: Ashish Singhal > Subject: [edk2] [PATCH v6 1/2] MdeModulePkg/SdMmcPciHcDxe: Declare V4 > 64 bit address capability >=20 > Add capability declaration for V4.x 64 bit system address support. > This would be used for host controllers working in version 4. Enable > 64 bit DMA support in PCI layer if V3 or V4 64 bit support is > enabled in host capability register. >=20 > The usage of this new field does not need a guard for version check as > spec for previous SDMMC versions defines this field as reserved with > default value of 0. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1359 >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ashish Singhal > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 9 ++++++++- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 3 ++- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 10 +++++----- > 3 files changed, 15 insertions(+), 7 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > index a87f8de..2bfd758 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > @@ -649,7 +649,14 @@ SdMmcPciHcDriverBindingStart ( > Private->BaseClkFreq[Slot] > )); >=20 > - Support64BitDma &=3D Private->Capability[Slot].SysBus64; > + // > + // If any of the slots does not support 64b system bus > + // do not enable 64b DMA in the PCI layer. > + // > + if (Private->Capability[Slot].SysBus64V3 =3D=3D 0 &&^M > + Private->Capability[Slot].SysBus64V4 =3D=3D 0) {^M > + Support64BitDma &=3D FALSE;^M The above lines seem not well-formatted at EOL. With the that addressed: Reviewed-by: Hao Wu Best Regards, Hao Wu > + } >=20 > Status =3D SdMmcHcGetMaxCurrent (PciIo, Slot, &Private- > >MaxCurrent[Slot]); > if (EFI_ERROR (Status)) { > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index ddf6dcf..598b6a3 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -45,7 +45,8 @@ DumpCapabilityReg ( > DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33= ? > "TRUE" : "FALSE")); > DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30= ? > "TRUE" : "FALSE")); > DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18= ? > "TRUE" : "FALSE")); > - DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 = ? > "TRUE" : "FALSE")); > + DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V= 4 ? > "TRUE" : "FALSE")); > + DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V= 3 ? > "TRUE" : "FALSE")); > DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt = ? > "TRUE" : "FALSE")); > DEBUG ((DEBUG_INFO, " SlotType ")); > if (Capability->SlotType =3D=3D 0x00) { > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > index dd45cbd..ad9ce64 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > @@ -129,24 +129,24 @@ typedef struct { > UINT32 Voltage33:1; // bit 24 > UINT32 Voltage30:1; // bit 25 > UINT32 Voltage18:1; // bit 26 > - UINT32 Reserved3:1; // bit 27 > - UINT32 SysBus64:1; // bit 28 > + UINT32 SysBus64V4:1; // bit 27 > + UINT32 SysBus64V3:1; // bit 28 > UINT32 AsyncInt:1; // bit 29 > UINT32 SlotType:2; // bit 30:31 > UINT32 Sdr50:1; // bit 32 > UINT32 Sdr104:1; // bit 33 > UINT32 Ddr50:1; // bit 34 > - UINT32 Reserved4:1; // bit 35 > + UINT32 Reserved3:1; // bit 35 > UINT32 DriverTypeA:1; // bit 36 > UINT32 DriverTypeC:1; // bit 37 > UINT32 DriverTypeD:1; // bit 38 > UINT32 DriverType4:1; // bit 39 > UINT32 TimerCount:4; // bit 40:43 > - UINT32 Reserved5:1; // bit 44 > + UINT32 Reserved4:1; // bit 44 > UINT32 TuningSDR50:1; // bit 45 > UINT32 RetuningMod:2; // bit 46:47 > UINT32 ClkMultiplier:8; // bit 48:55 > - UINT32 Reserved6:7; // bit 56:62 > + UINT32 Reserved5:7; // bit 56:62 > UINT32 Hs400:1; // bit 63 > } SD_MMC_HC_SLOT_CAP; >=20 > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel