From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F0CF7211C573E for ; Thu, 31 Jan 2019 21:55:38 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Jan 2019 21:55:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,547,1539673200"; d="scan'208";a="130278383" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by FMSMGA003.fm.intel.com with ESMTP; 31 Jan 2019 21:55:38 -0800 Received: from fmsmsx120.amr.corp.intel.com (10.18.124.208) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 31 Jan 2019 21:55:38 -0800 Received: from shsmsx107.ccr.corp.intel.com (10.239.4.96) by fmsmsx120.amr.corp.intel.com (10.18.124.208) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 31 Jan 2019 21:55:37 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.102]) by SHSMSX107.ccr.corp.intel.com ([169.254.9.162]) with mapi id 14.03.0415.000; Fri, 1 Feb 2019 13:55:36 +0800 From: "Wu, Hao A" To: Jeff Brasen , "edk2-devel@lists.01.org" CC: Edgar Handal Thread-Topic: [edk2] [PATCH] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths Thread-Index: AQHUuPfkGoiAfNeKak+Wm9jQVLNaX6XKci6w Date: Fri, 1 Feb 2019 05:55:35 +0000 Message-ID: References: <7a0d5c95fdeee0e68f54c8a6a0fbe37c85e76774.1548892644.git.jbrasen@nvidia.com> In-Reply-To: <7a0d5c95fdeee0e68f54c8a6a0fbe37c85e76774.1548892644.git.jbrasen@nvidia.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Feb 2019 05:55:39 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Je= ff > Brasen > Sent: Thursday, January 31, 2019 7:59 AM > To: edk2-devel@lists.01.org > Cc: Edgar Handal; Jeff Brasen > Subject: [edk2] [PATCH] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO > widths >=20 > From: Edgar Handal >=20 > Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register > accesses from being split up into 8-bit accesses. >=20 > The SDHCI specification states that the registers shall be accessable in > byte, word, and double word accesses. Hi, Thanks for the contribution. The change seems good to me. Just curious, if the accesses are always slit into byte(8-bit), is there an= y issue or performance impact is encountered during your usage? It will be helpful to get more information on the purpose of the patch. Thanks. Best Regards, Hao Wu >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jeff Brasen > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 25 > ++++++++++++++++++++---- > 1 file changed, 21 insertions(+), 4 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index 5aec8c6..82f4493 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -152,19 +152,36 @@ SdMmcHcRwMmio ( > ) > { > EFI_STATUS Status; > + EFI_PCI_IO_PROTOCOL_WIDTH Width; >=20 > if ((PciIo =3D=3D NULL) || (Data =3D=3D NULL)) { > return EFI_INVALID_PARAMETER; > } >=20 > - if ((Count !=3D 1) && (Count !=3D 2) && (Count !=3D 4) && (Count !=3D = 8)) { > - return EFI_INVALID_PARAMETER; > + switch (Count) { > + case 1: > + Width =3D EfiPciIoWidthUint8; > + break; > + case 2: > + Width =3D EfiPciIoWidthUint16; > + Count =3D 1; > + break; > + case 4: > + Width =3D EfiPciIoWidthUint32; > + Count =3D 1; > + break; > + case 8: > + Width =3D EfiPciIoWidthUint32; > + Count =3D 2; > + break; > + default: > + return EFI_INVALID_PARAMETER; > } >=20 > if (Read) { > Status =3D PciIo->Mem.Read ( > PciIo, > - EfiPciIoWidthUint8, > + Width, > BarIndex, > (UINT64) Offset, > Count, > @@ -173,7 +190,7 @@ SdMmcHcRwMmio ( > } else { > Status =3D PciIo->Mem.Write ( > PciIo, > - EfiPciIoWidthUint8, > + Width, > BarIndex, > (UINT64) Offset, > Count, > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel