From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C06BA20886F46 for ; Sun, 17 Feb 2019 22:00:53 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Feb 2019 22:00:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,383,1544515200"; d="scan'208";a="321214881" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga005.fm.intel.com with ESMTP; 17 Feb 2019 22:00:52 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sun, 17 Feb 2019 22:00:52 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.102]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.109]) with mapi id 14.03.0415.000; Mon, 18 Feb 2019 14:00:50 +0800 From: "Wu, Hao A" To: "Albecki, Mateusz" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 switch sequence Thread-Index: AQHUxT0TxoRse28Mpkqmkftod8a+OqXlEEKw Date: Mon, 18 Feb 2019 06:00:50 +0000 Message-ID: References: <20190215144458.1812-1-mateusz.albecki@intel.com> <20190215144458.1812-2-mateusz.albecki@intel.com> In-Reply-To: <20190215144458.1812-2-mateusz.albecki@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 switch sequence X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Feb 2019 06:00:54 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Mateusz, I found that the patch proposed is actually handling one of the issues reported in the below BZ tracker: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1140 According to the discussion within the tracker, there are 2 fixes needed for the SdMmcPciHcDxe: 1. Move the clock supply before doing send status 2. More robust handle to the send status CRC error on the switch to HS200 I think the proposed patch is handling the 1st issue listed above. So could you help to add the below line: REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1140 at the beginning of your commit log message? Also, please see the below inline comments below: > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Albecki, Mateusz > Sent: Friday, February 15, 2019 10:45 PM > To: edk2-devel@lists.01.org > Cc: Wu, Hao A > Subject: [edk2] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe Fix eMMC > HS400 switch sequence >=20 > In eMMC HS400 switch sequence flow eMMC driver attampted 'attampted' -> 'attempted' > to execute SEND_STATUS just after switching bus timing to high > speed and before downgrading clock frequency to 52MHz. Since link > was at that time in incorrect state SEND_STATUS was failing which > made driver think switch to HS400 failed. > This change makes driver always change clock frequency after > switching bus timing and before executing SEND_STATUS. >=20 > Change-Id: Ib1f2c78a8693c2a4ef6e1f1b5da2f4133f6210d2 Please help to remove the above 'Change-Id' information. > Cc: Hao Wu > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Albecki Mateusz > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 37 > +++++++++++++------------ > 1 file changed, 19 insertions(+), 18 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > index 4ef849fd0962..22200f806f26 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > @@ -642,7 +642,7 @@ EmmcSwitchBusWidth ( > } >=20 > /** > - Switch the clock frequency to the specified value. > + Switch the bus timing and clock frequency. >=20 > Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host > Controller > Simplified Spec 3.0 Figure 3-3 for details. > @@ -660,7 +660,7 @@ EmmcSwitchBusWidth ( >=20 > **/ > EFI_STATUS > -EmmcSwitchClockFreq ( > +EmmcSwitchBusTiming ( Could you help to update the debug messages that include keyword 'EmmcSwitchClockFreq' to 'EmmcSwitchBusTiming' to align with the function name change? Best Regards, Hao Wu > IN EFI_PCI_IO_PROTOCOL *PciIo, > IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, > IN UINT8 Slot, > @@ -693,18 +693,6 @@ EmmcSwitchClockFreq ( > return Status; > } >=20 > - Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); > - if (EFI_ERROR (Status)) { > - DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: Send status fails > with %r\n", Status)); > - return Status; > - } > - // > - // Check the switch operation is really successful or not. > - // > - if ((DevStatus & BIT7) !=3D 0) { > - DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: The switch operation > fails as DevStatus is 0x%08x\n", DevStatus)); > - return EFI_DEVICE_ERROR; > - } > // > // Convert the clock freq unit from MHz to KHz. > // > @@ -713,6 +701,19 @@ EmmcSwitchClockFreq ( > return Status; > } >=20 > + Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: Send status fails > with %r\n", Status)); > + return Status; > + } > + // > + // Check the switch operation is really successful or not. > + // > + if ((DevStatus & BIT7) !=3D 0) { > + DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: The switch operation > fails as DevStatus is 0x%08x\n", DevStatus)); > + return EFI_DEVICE_ERROR; > + } > + > if (mOverride !=3D NULL && mOverride->NotifyPhase !=3D NULL) { > Status =3D mOverride->NotifyPhase ( > Private->ControllerHandle, > @@ -799,7 +800,7 @@ EmmcSwitchToHighSpeed ( > } >=20 > HsTiming =3D 1; > - Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, = Timing, > ClockFreq); > + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, > Timing, ClockFreq); >=20 > return Status; > } > @@ -887,7 +888,7 @@ EmmcSwitchToHS200 ( > Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof > (ClockCtrl), &ClockCtrl); >=20 > HsTiming =3D 2; > - Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, = Timing, > ClockFreq); > + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, > Timing, ClockFreq); > if (EFI_ERROR (Status)) { > return Status; > } > @@ -937,7 +938,7 @@ EmmcSwitchToHS400 ( > // Set to Hight Speed timing and set the clock frequency to a value le= ss than > 52MHz. > // > HsTiming =3D 1; > - Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, > SdMmcMmcHsSdr, 52); > + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, > SdMmcMmcHsSdr, 52); > if (EFI_ERROR (Status)) { > return Status; > } > @@ -957,7 +958,7 @@ EmmcSwitchToHS400 ( > } >=20 > HsTiming =3D 3; > - Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, = Timing, > ClockFreq); > + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, > Timing, ClockFreq); >=20 > return Status; > } > -- > 2.14.1.windows.1 >=20 > -------------------------------------------------------------------- >=20 > Intel Technology Poland sp. z o.o. > ul. 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