From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C2FD02194EB76 for ; Tue, 19 Feb 2019 17:11:27 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Feb 2019 17:11:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,388,1544515200"; d="scan'208";a="320425252" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga006.fm.intel.com with ESMTP; 19 Feb 2019 17:11:26 -0800 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 19 Feb 2019 17:11:26 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 19 Feb 2019 17:11:26 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.102]) by shsmsx102.ccr.corp.intel.com ([169.254.2.207]) with mapi id 14.03.0415.000; Wed, 20 Feb 2019 09:11:25 +0800 From: "Wu, Hao A" To: "Albecki, Mateusz" , "edk2-devel@lists.01.org" Thread-Topic: [PATCHv2 1/1] MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 switch sequence Thread-Index: AQHUx3rIy8f3+NyslkiJXxh6+lFrPaXmTKbg Date: Wed, 20 Feb 2019 01:11:24 +0000 Message-ID: References: In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCHv2 1/1] MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 switch sequence X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Feb 2019 01:11:28 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Mateusz, Reviewed-by: Hao Wu And pushed via commit 68c67d3a2a33261e41ff0123129b4e9759617f71. Best Regards, Hao Wu > -----Original Message----- > From: Albecki, Mateusz > Sent: Monday, February 18, 2019 7:12 PM > To: edk2-devel@lists.01.org > Cc: Albecki, Mateusz; Wu, Hao A > Subject: [PATCHv2 1/1] MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 > switch sequence >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1140 >=20 > In eMMC HS400 switch sequence flow eMMC driver attempted > to execute SEND_STATUS just after switching bus timing to high > speed and before downgrading clock frequency to 52MHz. Since link > was at that time in incorrect state SEND_STATUS was failing which > made driver think switch to HS400 failed. > This change makes driver always change clock frequency after > switching bus timing and before executing SEND_STATUS. >=20 > Cc: Hao Wu > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Albecki Mateusz > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 39 > +++++++++++++------------ > 1 file changed, 20 insertions(+), 19 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > index 4ef849fd0962..15db8a87a5c4 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > @@ -642,7 +642,7 @@ EmmcSwitchBusWidth ( > } >=20 > /** > - Switch the clock frequency to the specified value. > + Switch the bus timing and clock frequency. >=20 > Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host > Controller > Simplified Spec 3.0 Figure 3-3 for details. > @@ -660,7 +660,7 @@ EmmcSwitchBusWidth ( >=20 > **/ > EFI_STATUS > -EmmcSwitchClockFreq ( > +EmmcSwitchBusTiming ( > IN EFI_PCI_IO_PROTOCOL *PciIo, > IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, > IN UINT8 Slot, > @@ -689,22 +689,10 @@ EmmcSwitchClockFreq ( >=20 > Status =3D EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet); > if (EFI_ERROR (Status)) { > - DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: Switch to hstiming %d > fails with %r\n", HsTiming, Status)); > + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Switch to hstiming %d > fails with %r\n", HsTiming, Status)); > return Status; > } >=20 > - Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); > - if (EFI_ERROR (Status)) { > - DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: Send status fails > with %r\n", Status)); > - return Status; > - } > - // > - // Check the switch operation is really successful or not. > - // > - if ((DevStatus & BIT7) !=3D 0) { > - DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: The switch operation > fails as DevStatus is 0x%08x\n", DevStatus)); > - return EFI_DEVICE_ERROR; > - } > // > // Convert the clock freq unit from MHz to KHz. > // > @@ -713,6 +701,19 @@ EmmcSwitchClockFreq ( > return Status; > } >=20 > + Status =3D EmmcSendStatus (PassThru, Slot, Rca, &DevStatus); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Send status fails > with %r\n", Status)); > + return Status; > + } > + // > + // Check the switch operation is really successful or not. > + // > + if ((DevStatus & BIT7) !=3D 0) { > + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: The switch operation > fails as DevStatus is 0x%08x\n", DevStatus)); > + return EFI_DEVICE_ERROR; > + } > + > if (mOverride !=3D NULL && mOverride->NotifyPhase !=3D NULL) { > Status =3D mOverride->NotifyPhase ( > Private->ControllerHandle, > @@ -799,7 +800,7 @@ EmmcSwitchToHighSpeed ( > } >=20 > HsTiming =3D 1; > - Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, = Timing, > ClockFreq); > + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, > Timing, ClockFreq); >=20 > return Status; > } > @@ -887,7 +888,7 @@ EmmcSwitchToHS200 ( > Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof > (ClockCtrl), &ClockCtrl); >=20 > HsTiming =3D 2; > - Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, = Timing, > ClockFreq); > + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, > Timing, ClockFreq); > if (EFI_ERROR (Status)) { > return Status; > } > @@ -937,7 +938,7 @@ EmmcSwitchToHS400 ( > // Set to Hight Speed timing and set the clock frequency to a value le= ss than > 52MHz. > // > HsTiming =3D 1; > - Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, > SdMmcMmcHsSdr, 52); > + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, > SdMmcMmcHsSdr, 52); > if (EFI_ERROR (Status)) { > return Status; > } > @@ -957,7 +958,7 @@ EmmcSwitchToHS400 ( > } >=20 > HsTiming =3D 3; > - Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, = Timing, > ClockFreq); > + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, > Timing, ClockFreq); >=20 > return Status; > } > -- > 2.14.1.windows.1