From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1F00520886F35 for ; Tue, 19 Feb 2019 17:12:12 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Feb 2019 17:12:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,388,1544515200"; d="scan'208";a="320425402" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga006.fm.intel.com with ESMTP; 19 Feb 2019 17:12:12 -0800 Received: from fmsmsx151.amr.corp.intel.com (10.18.125.4) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 19 Feb 2019 17:12:12 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX151.amr.corp.intel.com (10.18.125.4) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 19 Feb 2019 17:12:11 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.102]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.110]) with mapi id 14.03.0415.000; Wed, 20 Feb 2019 09:12:10 +0800 From: "Wu, Hao A" To: Jeff Brasen , "edk2-devel@lists.01.org" CC: Edgar Handal Thread-Topic: [PATCH v2] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths Thread-Index: AQHUyHWXP8mJNsLte0eoq15vfZF8oqXn4X7A Date: Wed, 20 Feb 2019 01:12:09 +0000 Message-ID: References: In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Feb 2019 01:12:13 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Jeff. Reviewed-by: Hao Wu And pushed via commit f168816c49e388dcd097dd62d766d63f73aaabb3. Best Regards, Hao Wu > -----Original Message----- > From: Jeff Brasen [mailto:jbrasen@nvidia.com] > Sent: Wednesday, February 20, 2019 1:07 AM > To: edk2-devel@lists.01.org > Cc: Edgar Handal; Jeff Brasen; Wu, Hao A > Subject: [PATCH v2] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO > widths >=20 > From: Edgar Handal >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1537 >=20 > Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register > accesses from being split up into 8-bit accesses. >=20 > The SDHCI specification states that the registers shall be accessible in > byte, word, and double word accesses. (SD Host Controller Simplified > Specification 4.20 Section 1.2) >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jeff Brasen > Cc: Hao A Wu > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 25 > ++++++++++++++++++++---- > 1 file changed, 21 insertions(+), 4 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index 4c64da3..d73fa10 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -154,19 +154,36 @@ SdMmcHcRwMmio ( > ) > { > EFI_STATUS Status; > + EFI_PCI_IO_PROTOCOL_WIDTH Width; >=20 > if ((PciIo =3D=3D NULL) || (Data =3D=3D NULL)) { > return EFI_INVALID_PARAMETER; > } >=20 > - if ((Count !=3D 1) && (Count !=3D 2) && (Count !=3D 4) && (Count !=3D = 8)) { > - return EFI_INVALID_PARAMETER; > + switch (Count) { > + case 1: > + Width =3D EfiPciIoWidthUint8; > + break; > + case 2: > + Width =3D EfiPciIoWidthUint16; > + Count =3D 1; > + break; > + case 4: > + Width =3D EfiPciIoWidthUint32; > + Count =3D 1; > + break; > + case 8: > + Width =3D EfiPciIoWidthUint32; > + Count =3D 2; > + break; > + default: > + return EFI_INVALID_PARAMETER; > } >=20 > if (Read) { > Status =3D PciIo->Mem.Read ( > PciIo, > - EfiPciIoWidthUint8, > + Width, > BarIndex, > (UINT64) Offset, > Count, > @@ -175,7 +192,7 @@ SdMmcHcRwMmio ( > } else { > Status =3D PciIo->Mem.Write ( > PciIo, > - EfiPciIoWidthUint8, > + Width, > BarIndex, > (UINT64) Offset, > Count, > -- > 2.7.4