From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9F6AA211BA45C for ; Wed, 27 Feb 2019 19:24:46 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2019 19:24:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,421,1544515200"; d="scan'208";a="136884231" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by FMSMGA003.fm.intel.com with ESMTP; 27 Feb 2019 19:24:45 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 27 Feb 2019 19:24:45 -0800 Received: from shsmsx153.ccr.corp.intel.com (10.239.6.53) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 27 Feb 2019 19:24:45 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.74]) by SHSMSX153.ccr.corp.intel.com ([169.254.12.121]) with mapi id 14.03.0415.000; Thu, 28 Feb 2019 11:24:43 +0800 From: "Wu, Hao A" To: "Cohen, Eugene" , "edk2-devel@lists.01.org" CC: Ashish Singhal Thread-Topic: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems Thread-Index: AdTOimUh6bq74L7bQyCZsF0hnADHfgAhuWlQ Date: Thu, 28 Feb 2019 03:24:42 +0000 Message-ID: References: In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Feb 2019 03:24:46 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Loop Ashish in. Some comments below. > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Cohen, Eugene > Sent: Wednesday, February 27, 2019 6:59 PM > To: edk2-devel@lists.01.org; Wu, Hao A > Subject: [edk2] [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC > v3 64-bit systems >=20 > The SdMmcPciHcDriverBindingStart function was checking two > different capability bits in determining whether 64-bit DMA > modes were supported, one mode is defined in the SDHC version > 3 specification (using 96-bit descriptors) and another is > defined in the SDHC version 4 specification (using 128-bit > descriptors). Since the currently implementation of 64-bit > ADMA2 only supports the SDHC version 4 implementation it is > incorrect to check the V3 64-bit capability bit since this > will activate V4 ADMA2 on V3 controllers. I remember the commit b5547b9ce97e80c3127682a2a5d4b9bd14af353e from Ashish only handles the controllers with version greater or equal to 4.00. And the ADMA2 (96-bit Descriptor) mode for V3 controllers is selected by setting the 'DMA Select' filed in the Host Control 1 Register to 11b. But the currently behavior of the driver is setting the field to 10b, which I think will not switch to the ADMA2 (96-bit Descriptor) mode for V3. Maybe there is something I miss here. Could you help to provide some more detail on the issue you met? Thanks. Best Regards, Hao Wu >=20 > Cc: Hao Wu > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eugene Cohen > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > index b474f8d..5bc91c5 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > @@ -666,8 +666,7 @@ SdMmcPciHcDriverBindingStart ( > // If any of the slots does not support 64b system bus > // do not enable 64b DMA in the PCI layer. > // > - if (Private->Capability[Slot].SysBus64V3 =3D=3D 0 && > - Private->Capability[Slot].SysBus64V4 =3D=3D 0) { > + if (Private->Capability[Slot].SysBus64V4 =3D=3D 0) { > Support64BitDma =3D FALSE; > } >=20 > -- > 2.7.4 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel