[PATCHv2 0/3] Fix eMMC bus timing switch issue

[PATCHv2 0/3] Fix eMMC bus timing switch issue

[Albecki, Mateusz]

SD host controller specification section 3.9 recommends that controller's bus timing
should be switched after card's bus timing has been switched. In current eMMC
driver implementation every host controller switch has been done before call to
EmmcSwitchBusTiming which is causing issues on some eMMC controllers.

In HS200 switch sequence we removed stopping and starting the SD clock when
switching the host controller timing. Stopping the clock before bus timing
switch is only neccessary if preset value enable is set in host controller.
Current code doesn't check if this field is enabled or doesn't support
this feature for any other bus timing change so it has been removed.

Third patch fixes issue with switch to SdMmcMmcLegacy speed mode that was
introduced when we implemented v3 of override protocol. In new flow we allowed
EmmcSwitchToHighSpeed to be called with SdMmcMmcLegacy since all of the logic
in that function is ready to service this speed mode.

Tests performed on patch series v1:
- eMMC enumeration and OS boot in HS400
- eMMC enumeration and OS boot in HS200
- eMMC enumeration and OS boot in high speed SDR 8bit @52MHz

Tests have been performed on 2 eMMC host controllers. One that has been failing
with old driver and one that has been passing with old driver. Both controllers
pass all tests with multiple eMMC devices used.

Note: We were unable to test DDR speed mode because on test machines both new flow
and old flow was failing with this speed. I suspect it is a hardware problem.

Tests performed on patch series v2:
-eMMC enumeration and OS boot in backwards compatible legacy timing.

Performed on single host controller and 2 eMMC devices(Samsung and SanDisk)

Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Marcin Wojtas <mw@semihalf.com>

Albecki, Mateusz (3):
  MdeModulePkg/SdMmcPciHcDxe: Remove clock stop and start from HS200
    switch
  MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence
  MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing handling

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 107 ++++++++----------------
 1 file changed, 33 insertions(+), 74 deletions(-)

-- 
2.14.1.windows.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.

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[PATCHv2 1/3] MdeModulePkg/SdMmcPciHcDxe: Remove clock stop from HS200 switch

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218

Stopping the SD clock before switching host controller
bus timing is only neccessary if preset value enable is
set in host controller. Code that performs switch to
HS200 doesn't check this condition right now and we also
don't do the SD clock stop before any other bus timing switch
in host controller. Since the driver is generally not ready to support
host controller with preset value enable set we removed this
code.

Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Marcin Wojtas <mw@semihalf.com>
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 29 -------------------------
 1 file changed, 29 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 3f4a8e5413..bd70490286 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -837,7 +837,6 @@ EmmcSwitchToHS200 (
   )
 {
   EFI_STATUS               Status;
-  UINT16                   ClockCtrl;
   SD_MMC_HC_PRIVATE_DATA  *Private;
 
   Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -851,40 +850,12 @@ EmmcSwitchToHS200 (
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  //
-  // Stop bus clock at first
-  //
-  Status = SdMmcHcStopClock (PciIo, Slot);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
 
   Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, BusMode->BusTiming);
   if (EFI_ERROR (Status)) {
     return Status;
   }
 
-  //
-  // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
-  //
-  Status = SdMmcHcWaitMmioSet (
-             PciIo,
-             Slot,
-             SD_MMC_HC_CLOCK_CTRL,
-             sizeof (ClockCtrl),
-             BIT1,
-             BIT1,
-             SD_MMC_HC_GENERIC_TIMEOUT
-             );
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-  //
-  // Set SD Clock Enable in the Clock Control register to 1
-  //
-  ClockCtrl = BIT2;
-  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
-
   Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
   if (EFI_ERROR (Status)) {
     return Status;
-- 
2.14.1.windows.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.

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others is strictly prohibited.

[PATCHv2 2/3] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218

SD specification recommends switching card bus timing before
switching bus timing in controller. Emmc driver used to do
this switch other way around. This commit adds controller
timing switch in EmmcSwitchBusTiming function to enforce this
order and removes all controller timing programing from
EmmcSwitchToXXX functions.

Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Marcin Wojtas <mw@semihalf.com>
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 70 +++++++++----------------
 1 file changed, 26 insertions(+), 44 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index bd70490286..3598a8538a 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -671,6 +671,7 @@ EmmcSwitchBusTiming (
   UINT8                     CmdSet;
   UINT32                    DevStatus;
   SD_MMC_HC_PRIVATE_DATA    *Private;
+  UINT8                     HostCtrl1;
 
   Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
   //
@@ -704,6 +705,25 @@ EmmcSwitchBusTiming (
     return Status;
   }
 
+  if (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcHsDdr) {
+    HostCtrl1 = BIT2;
+    Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  } else {
+    HostCtrl1 = (UINT8)~BIT2;
+    Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+
+  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, BusTiming);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
   //
   // Convert the clock freq unit from MHz to KHz.
   //
@@ -771,12 +791,8 @@ EmmcSwitchToHighSpeed (
   IN SD_MMC_BUS_SETTINGS                *BusMode
   )
 {
-  EFI_STATUS              Status;
-  UINT8                   HostCtrl1;
-  SD_MMC_HC_PRIVATE_DATA  *Private;
-  BOOLEAN                 IsDdr;
-
-  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  EFI_STATUS  Status;
+  BOOLEAN     IsDdr;
 
   if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != SdMmcMmcHsDdr) ||
       BusMode->ClockFreq > 52) {
@@ -794,20 +810,6 @@ EmmcSwitchToHighSpeed (
     return Status;
   }
 
-  //
-  // Set to High Speed timing
-  //
-  HostCtrl1 = BIT2;
-  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, BusMode->BusTiming);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
   return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
 }
 
@@ -836,10 +838,7 @@ EmmcSwitchToHS200 (
   IN SD_MMC_BUS_SETTINGS                *BusMode
   )
 {
-  EFI_STATUS               Status;
-  SD_MMC_HC_PRIVATE_DATA  *Private;
-
-  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  EFI_STATUS  Status;
 
   if (BusMode->BusTiming != SdMmcMmcHs200 ||
       (BusMode->BusWidth != 4 && BusMode->BusWidth != 8)) {
@@ -851,11 +850,6 @@ EmmcSwitchToHS200 (
     return Status;
   }
 
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, BusMode->BusTiming);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
   Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
   if (EFI_ERROR (Status)) {
     return Status;
@@ -891,17 +885,15 @@ EmmcSwitchToHS400 (
   IN SD_MMC_BUS_SETTINGS                *BusMode
   )
 {
-  EFI_STATUS                 Status;
-  SD_MMC_HC_PRIVATE_DATA     *Private;
-  SD_MMC_BUS_SETTINGS        Hs200BusMode;
-  UINT32                     HsFreq;
+  EFI_STATUS           Status;
+  SD_MMC_BUS_SETTINGS  Hs200BusMode;
+  UINT32               HsFreq;
 
   if (BusMode->BusTiming != SdMmcMmcHs400 ||
       BusMode->BusWidth != 8) {
     return EFI_INVALID_PARAMETER;
   }
 
-  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
   Hs200BusMode.BusTiming = SdMmcMmcHs200;
   Hs200BusMode.BusWidth = BusMode->BusWidth;
   Hs200BusMode.ClockFreq = BusMode->ClockFreq;
@@ -916,11 +908,6 @@ EmmcSwitchToHS400 (
   // Set to High Speed timing and set the clock frequency to a value less than or equal to 52MHz.
   // This step is necessary to be able to switch Bus into 8 bit DDR mode which is unsupported in HS200.
   //
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, SdMmcMmcHsSdr);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
   HsFreq = BusMode->ClockFreq < 52 ? BusMode->ClockFreq : 52;
   Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, SdMmcMmcHsSdr, HsFreq);
   if (EFI_ERROR (Status)) {
@@ -932,11 +919,6 @@ EmmcSwitchToHS400 (
     return Status;
   }
 
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, BusMode->BusTiming);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
   return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
 }
 
-- 
2.14.1.windows.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek
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others is strictly prohibited.

[PATCHv2 3/3] MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing handling

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218

There is a bug in current driver code that makes
it impossible for it to work with devices that
only work in legacy speed mode since the function
EmmcSwitchToHighSpeed will return with EFI_INVALID_ARGUMENT
for such bus mode. Since the logic in that function will
work well for SdMmcMmcLegacy this patch just allows
to call this function with SdMmcMmcLegacy bus mode.

Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Marcin Wojtas <mw@semihalf.com>
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 3598a8538a..082904ccc5 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -794,7 +794,7 @@ EmmcSwitchToHighSpeed (
   EFI_STATUS  Status;
   BOOLEAN     IsDdr;
 
-  if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != SdMmcMmcHsDdr) ||
+  if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != SdMmcMmcHsDdr && BusMode->BusTiming != SdMmcMmcLegacy) ||
       BusMode->ClockFreq > 52) {
     return EFI_INVALID_PARAMETER;
   }
@@ -1244,6 +1244,12 @@ EmmcSetBusMode (
   } else if (BusMode.BusTiming == SdMmcMmcHs200) {
     Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, &BusMode);
   } else {
+    //
+    // Note that EmmcSwitchToHighSpeed is also called for SdMmcMmcLegacy
+    // bus timing. This is because even though we might not want to
+    // change the timing itself we still want to allow customization of
+    // bus parameters such as clock frequency and bus width.
+    //
     Status = EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, &BusMode);
   }
 
-- 
2.14.1.windows.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek
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others is strictly prohibited.

Re: [PATCHv2 0/3] Fix eMMC bus timing switch issue

[Wu, Hao A]

> -----Original Message-----
> From: Albecki, Mateusz
> Sent: Thursday, September 26, 2019 10:28 PM
> To: devel@edk2.groups.io
> Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas
> Subject: [PATCHv2 0/3] Fix eMMC bus timing switch issue
> 
> SD host controller specification section 3.9 recommends that controller's bus
> timing
> should be switched after card's bus timing has been switched. In current
> eMMC
> driver implementation every host controller switch has been done before call
> to
> EmmcSwitchBusTiming which is causing issues on some eMMC controllers.
> 
> In HS200 switch sequence we removed stopping and starting the SD clock
> when
> switching the host controller timing. Stopping the clock before bus timing
> switch is only neccessary if preset value enable is set in host controller.
> Current code doesn't check if this field is enabled or doesn't support
> this feature for any other bus timing change so it has been removed.
> 
> Third patch fixes issue with switch to SdMmcMmcLegacy speed mode that
> was
> introduced when we implemented v3 of override protocol. In new flow we
> allowed
> EmmcSwitchToHighSpeed to be called with SdMmcMmcLegacy since all of
> the logic
> in that function is ready to service this speed mode.
> 
> Tests performed on patch series v1:
> - eMMC enumeration and OS boot in HS400
> - eMMC enumeration and OS boot in HS200
> - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz
> 
> Tests have been performed on 2 eMMC host controllers. One that has been
> failing
> with old driver and one that has been passing with old driver. Both
> controllers
> pass all tests with multiple eMMC devices used.
> 
> Note: We were unable to test DDR speed mode because on test machines
> both new flow
> and old flow was failing with this speed. I suspect it is a hardware problem.
> 
> Tests performed on patch series v2:
> -eMMC enumeration and OS boot in backwards compatible legacy timing.
> 
> Performed on single host controller and 2 eMMC devices(Samsung and
> SanDisk)
> 
> Cc: Hao A Wu <hao.a.wu@intel.com>
> Cc: Marcin Wojtas <mw@semihalf.com>


For the embedded eMMC on Intel Leaf Hill board, all of the below bus timing
modes are verified:
HS400
HS200
High Speed DDR
High Speed SDR
Legacy MMC

For the series,
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Tested-by: Hao A Wu <hao.a.wu@intel.com>

I will wait for comments from Marcin before pushing this series.

Best Regards,
Hao Wu


> 
> Albecki, Mateusz (3):
>   MdeModulePkg/SdMmcPciHcDxe: Remove clock stop and start from HS200
>     switch
>   MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence
>   MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing
> handling
> 
>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 107 ++++++++--
> --------------
>  1 file changed, 33 insertions(+), 74 deletions(-)
> 
> --
> 2.14.1.windows.1

Re: [edk2-devel] [PATCHv2 0/3] Fix eMMC bus timing switch issue

[Wu, Hao A]

> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Wu, Hao A
> Sent: Friday, September 27, 2019 10:50 AM
> To: Albecki, Mateusz; devel@edk2.groups.io
> Cc: Marcin Wojtas
> Subject: Re: [edk2-devel] [PATCHv2 0/3] Fix eMMC bus timing switch issue
> 
> > -----Original Message-----
> > From: Albecki, Mateusz
> > Sent: Thursday, September 26, 2019 10:28 PM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas
> > Subject: [PATCHv2 0/3] Fix eMMC bus timing switch issue
> >
> > SD host controller specification section 3.9 recommends that controller's
> bus
> > timing
> > should be switched after card's bus timing has been switched. In current
> > eMMC
> > driver implementation every host controller switch has been done before
> call
> > to
> > EmmcSwitchBusTiming which is causing issues on some eMMC controllers.
> >
> > In HS200 switch sequence we removed stopping and starting the SD clock
> > when
> > switching the host controller timing. Stopping the clock before bus timing
> > switch is only neccessary if preset value enable is set in host controller.
> > Current code doesn't check if this field is enabled or doesn't support
> > this feature for any other bus timing change so it has been removed.
> >
> > Third patch fixes issue with switch to SdMmcMmcLegacy speed mode that
> > was
> > introduced when we implemented v3 of override protocol. In new flow we
> > allowed
> > EmmcSwitchToHighSpeed to be called with SdMmcMmcLegacy since all of
> > the logic
> > in that function is ready to service this speed mode.
> >
> > Tests performed on patch series v1:
> > - eMMC enumeration and OS boot in HS400
> > - eMMC enumeration and OS boot in HS200
> > - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz
> >
> > Tests have been performed on 2 eMMC host controllers. One that has
> been
> > failing
> > with old driver and one that has been passing with old driver. Both
> > controllers
> > pass all tests with multiple eMMC devices used.
> >
> > Note: We were unable to test DDR speed mode because on test machines
> > both new flow
> > and old flow was failing with this speed. I suspect it is a hardware problem.
> >
> > Tests performed on patch series v2:
> > -eMMC enumeration and OS boot in backwards compatible legacy timing.
> >
> > Performed on single host controller and 2 eMMC devices(Samsung and
> > SanDisk)
> >
> > Cc: Hao A Wu <hao.a.wu@intel.com>
> > Cc: Marcin Wojtas <mw@semihalf.com>
> 
> 
> For the embedded eMMC on Intel Leaf Hill board, all of the below bus timing
> modes are verified:
> HS400
> HS200
> High Speed DDR
> High Speed SDR
> Legacy MMC
> 
> For the series,
> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
> Tested-by: Hao A Wu <hao.a.wu@intel.com>
> 
> I will wait for comments from Marcin before pushing this series.


Thanks Marcin for the help for the test verification:
https://edk2.groups.io/g/devel/message/48222

The series has been pushed via commits e86664d2b0..76e1e5631f.

Best Regards,
Hao Wu


> 
> Best Regards,
> Hao Wu
> 
> 
> >
> > Albecki, Mateusz (3):
> >   MdeModulePkg/SdMmcPciHcDxe: Remove clock stop and start from
> HS200
> >     switch
> >   MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence
> >   MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing
> > handling
> >
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 107
> ++++++++--
> > --------------
> >  1 file changed, 33 insertions(+), 74 deletions(-)
> >
> > --
> > 2.14.1.windows.1
> 
> 
>