From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: hao.a.wu@intel.com) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by groups.io with SMTP; Thu, 26 Sep 2019 19:50:01 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2019 19:50:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,553,1559545200"; d="scan'208";a="183833695" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga008.jf.intel.com with ESMTP; 26 Sep 2019 19:50:00 -0700 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 26 Sep 2019 19:50:00 -0700 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 26 Sep 2019 19:50:00 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.32]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.195]) with mapi id 14.03.0439.000; Fri, 27 Sep 2019 10:49:57 +0800 From: "Wu, Hao A" To: "Albecki, Mateusz" , "devel@edk2.groups.io" CC: Marcin Wojtas Subject: Re: [PATCHv2 0/3] Fix eMMC bus timing switch issue Thread-Topic: [PATCHv2 0/3] Fix eMMC bus timing switch issue Thread-Index: AQHVdHag/fLn/Dgn1Eaa3cCoUspSJ6c+0aSA Date: Fri, 27 Sep 2019 02:49:56 +0000 Message-ID: References: <20190926142744.3356-1-mateusz.albecki@intel.com> In-Reply-To: <20190926142744.3356-1-mateusz.albecki@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: hao.a.wu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Albecki, Mateusz > Sent: Thursday, September 26, 2019 10:28 PM > To: devel@edk2.groups.io > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas > Subject: [PATCHv2 0/3] Fix eMMC bus timing switch issue >=20 > SD host controller specification section 3.9 recommends that controller's= bus > timing > should be switched after card's bus timing has been switched. In current > eMMC > driver implementation every host controller switch has been done before c= all > to > EmmcSwitchBusTiming which is causing issues on some eMMC controllers. >=20 > In HS200 switch sequence we removed stopping and starting the SD clock > when > switching the host controller timing. Stopping the clock before bus timin= g > switch is only neccessary if preset value enable is set in host controlle= r. > Current code doesn't check if this field is enabled or doesn't support > this feature for any other bus timing change so it has been removed. >=20 > Third patch fixes issue with switch to SdMmcMmcLegacy speed mode that > was > introduced when we implemented v3 of override protocol. In new flow we > allowed > EmmcSwitchToHighSpeed to be called with SdMmcMmcLegacy since all of > the logic > in that function is ready to service this speed mode. >=20 > Tests performed on patch series v1: > - eMMC enumeration and OS boot in HS400 > - eMMC enumeration and OS boot in HS200 > - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz >=20 > Tests have been performed on 2 eMMC host controllers. One that has been > failing > with old driver and one that has been passing with old driver. Both > controllers > pass all tests with multiple eMMC devices used. >=20 > Note: We were unable to test DDR speed mode because on test machines > both new flow > and old flow was failing with this speed. I suspect it is a hardware prob= lem. >=20 > Tests performed on patch series v2: > -eMMC enumeration and OS boot in backwards compatible legacy timing. >=20 > Performed on single host controller and 2 eMMC devices(Samsung and > SanDisk) >=20 > Cc: Hao A Wu > Cc: Marcin Wojtas For the embedded eMMC on Intel Leaf Hill board, all of the below bus timing modes are verified: HS400 HS200 High Speed DDR High Speed SDR Legacy MMC For the series, Reviewed-by: Hao A Wu Tested-by: Hao A Wu I will wait for comments from Marcin before pushing this series. Best Regards, Hao Wu >=20 > Albecki, Mateusz (3): > MdeModulePkg/SdMmcPciHcDxe: Remove clock stop and start from HS200 > switch > MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence > MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing > handling >=20 > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 107 ++++++++-- > -------------- > 1 file changed, 33 insertions(+), 74 deletions(-) >=20 > -- > 2.14.1.windows.1