From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: hao.a.wu@intel.com) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by groups.io with SMTP; Sat, 28 Sep 2019 18:17:25 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Sep 2019 18:17:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,561,1559545200"; d="scan'208";a="204496877" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga001.fm.intel.com with ESMTP; 28 Sep 2019 18:17:24 -0700 Received: from fmsmsx157.amr.corp.intel.com (10.18.116.73) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sat, 28 Sep 2019 18:17:24 -0700 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by FMSMSX157.amr.corp.intel.com (10.18.116.73) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sat, 28 Sep 2019 18:17:24 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.166]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.225]) with mapi id 14.03.0439.000; Sun, 29 Sep 2019 09:17:21 +0800 From: "Wu, Hao A" To: "devel@edk2.groups.io" , "Wu, Hao A" , "Albecki, Mateusz" CC: Marcin Wojtas Subject: Re: [edk2-devel] [PATCHv2 0/3] Fix eMMC bus timing switch issue Thread-Topic: [edk2-devel] [PATCHv2 0/3] Fix eMMC bus timing switch issue Thread-Index: AQHVdHag/fLn/Dgn1Eaa3cCoUspSJ6c+0aSAgAMMGsA= Date: Sun, 29 Sep 2019 01:17:21 +0000 Message-ID: References: <20190926142744.3356-1-mateusz.albecki@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: hao.a.wu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Wu, Hao A > Sent: Friday, September 27, 2019 10:50 AM > To: Albecki, Mateusz; devel@edk2.groups.io > Cc: Marcin Wojtas > Subject: Re: [edk2-devel] [PATCHv2 0/3] Fix eMMC bus timing switch issue >=20 > > -----Original Message----- > > From: Albecki, Mateusz > > Sent: Thursday, September 26, 2019 10:28 PM > > To: devel@edk2.groups.io > > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas > > Subject: [PATCHv2 0/3] Fix eMMC bus timing switch issue > > > > SD host controller specification section 3.9 recommends that controlle= r's > bus > > timing > > should be switched after card's bus timing has been switched. In curre= nt > > eMMC > > driver implementation every host controller switch has been done befor= e > call > > to > > EmmcSwitchBusTiming which is causing issues on some eMMC controllers. > > > > In HS200 switch sequence we removed stopping and starting the SD clock > > when > > switching the host controller timing. Stopping the clock before bus ti= ming > > switch is only neccessary if preset value enable is set in host contro= ller. > > Current code doesn't check if this field is enabled or doesn't support > > this feature for any other bus timing change so it has been removed. > > > > Third patch fixes issue with switch to SdMmcMmcLegacy speed mode that > > was > > introduced when we implemented v3 of override protocol. In new flow we > > allowed > > EmmcSwitchToHighSpeed to be called with SdMmcMmcLegacy since all of > > the logic > > in that function is ready to service this speed mode. > > > > Tests performed on patch series v1: > > - eMMC enumeration and OS boot in HS400 > > - eMMC enumeration and OS boot in HS200 > > - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz > > > > Tests have been performed on 2 eMMC host controllers. One that has > been > > failing > > with old driver and one that has been passing with old driver. Both > > controllers > > pass all tests with multiple eMMC devices used. > > > > Note: We were unable to test DDR speed mode because on test machines > > both new flow > > and old flow was failing with this speed. I suspect it is a hardware p= roblem. > > > > Tests performed on patch series v2: > > -eMMC enumeration and OS boot in backwards compatible legacy timing. > > > > Performed on single host controller and 2 eMMC devices(Samsung and > > SanDisk) > > > > Cc: Hao A Wu > > Cc: Marcin Wojtas >=20 >=20 > For the embedded eMMC on Intel Leaf Hill board, all of the below bus tim= ing > modes are verified: > HS400 > HS200 > High Speed DDR > High Speed SDR > Legacy MMC >=20 > For the series, > Reviewed-by: Hao A Wu > Tested-by: Hao A Wu >=20 > I will wait for comments from Marcin before pushing this series. Thanks Marcin for the help for the test verification: https://edk2.groups.io/g/devel/message/48222 The series has been pushed via commits e86664d2b0..76e1e5631f. Best Regards, Hao Wu >=20 > Best Regards, > Hao Wu >=20 >=20 > > > > Albecki, Mateusz (3): > > MdeModulePkg/SdMmcPciHcDxe: Remove clock stop and start from > HS200 > > switch > > MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence > > MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing > > handling > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 107 > ++++++++-- > > -------------- > > 1 file changed, 33 insertions(+), 74 deletions(-) > > > > -- > > 2.14.1.windows.1 >=20 >=20 >=20