From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web12.469.1571619759015495977 for ; Sun, 20 Oct 2019 18:02:39 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: hao.a.wu@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Oct 2019 18:02:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,321,1566889200"; d="scan'208";a="372028438" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga005.jf.intel.com with ESMTP; 20 Oct 2019 18:02:37 -0700 Received: from fmsmsx605.amr.corp.intel.com (10.18.126.85) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 20 Oct 2019 18:02:37 -0700 Received: from fmsmsx605.amr.corp.intel.com (10.18.126.85) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Sun, 20 Oct 2019 18:02:37 -0700 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Sun, 20 Oct 2019 18:02:37 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.166]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.225]) with mapi id 14.03.0439.000; Mon, 21 Oct 2019 09:02:35 +0800 From: "Wu, Hao A" To: "devel@edk2.groups.io" , "ashishsingha@nvidia.com" , "Ni, Ray" , "jbrasen@nvidia.com" Subject: Re: [edk2-devel] [PATCH v4 0/2] Fix Aligned Page Allocation For XHCI Thread-Topic: [edk2-devel] [PATCH v4 0/2] Fix Aligned Page Allocation For XHCI Thread-Index: AQHVg3zsgaDdnPNq3kCaU/EVahs8H6dkTzpQ Date: Mon, 21 Oct 2019 01:02:34 +0000 Message-ID: References: In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: hao.a.wu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Ashish Singhal > Sent: Wednesday, October 16, 2019 1:21 AM > To: devel@edk2.groups.io; Wu, Hao A; Ni, Ray; jbrasen@nvidia.com > Cc: Ashish Singhal > Subject: [edk2-devel] [PATCH v4 0/2] Fix Aligned Page Allocation For XHC= I >=20 > This patch set is an attempt to fix the error where we allocate incorrec= tly > aligned memory for XHCI PEI and DXE. The change for DXE phase has been > verified > already but change for PEI needs to be verified by Hao as I do not have = a > setup to be able to verify that. >=20 > The change in DXE just updates a parameter passed in to allocate aligned > memory. > The change in PEI adds a new function to allocate aligned memory. There = was > no > need to add separate function to free aligned pages as unaligned pages h= ave > been > already freed during allocation function and the aligned one can be free= d > using > the existing function. >=20 > Ashish Singhal (2): > MdeModulePkg/XhciDxe: Fix Aligned Page Allocation > MdeModulePkg/XhciPei: Fix Aligned Page Allocation >=20 > MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 2 +- > MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c | 128 > ++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c | 25 +------ > MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h | 28 +++++++ > 4 files changed, 161 insertions(+), 22 deletions(-) Thanks for resolving the issues. Series pushed via commits 0f28c513d3..2bbbdeeea2. Best Regards, Hao Wu >=20 > -- > 2.7.4 >=20 >=20 >=20