From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web12.26581.1577671096312774604 for ; Sun, 29 Dec 2019 17:58:16 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: hao.a.wu@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Dec 2019 17:58:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,373,1571727600"; d="scan'208";a="220573348" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga006.jf.intel.com with ESMTP; 29 Dec 2019 17:58:15 -0800 Received: from fmsmsx605.amr.corp.intel.com (10.18.126.85) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 29 Dec 2019 17:58:15 -0800 Received: from fmsmsx605.amr.corp.intel.com (10.18.126.85) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Sun, 29 Dec 2019 17:58:14 -0800 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Sun, 29 Dec 2019 17:58:14 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.197]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.39]) with mapi id 14.03.0439.000; Mon, 30 Dec 2019 09:58:13 +0800 From: "Wu, Hao A" To: "Dong, Eric" , "devel@edk2.groups.io" CC: "Ni, Ray" , Laszlo Ersek , "Zeng, Star" , "Fu, Siyuan" , "Kinney, Michael D" Subject: Re: [PATCH v4 2/6] UefiCpuPkg/MpInitLib: Reduce the size when loading microcode patches Thread-Topic: [PATCH v4 2/6] UefiCpuPkg/MpInitLib: Reduce the size when loading microcode patches Thread-Index: AQHVvIfTWzOIHnV64EmHTtTFug5ri6fRaGeAgACG6JA= Date: Mon, 30 Dec 2019 01:58:13 +0000 Message-ID: References: <20191227073229.9416-1-hao.a.wu@intel.com> <20191227073229.9416-3-hao.a.wu@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: hao.a.wu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > > + > > + if (NeedLoad) { > > + PatchCount++; >=20 > [[Eric]] This logic seems not good. Image one case when PatchCount =3D=3D= 7 and > MaxPatchNumber =3D=3D 8. In this case, current logic needs to allocate ne= w buffer > for PatchInfoBuffer, but actually PatchInfoBuffer should be enough for th= is case. > So I think "PatchCount++;" code should move after " TotalLoadSize +=3D > PatchInfoBuffer[PatchCount - 1].AlignedSize;" and later " PatchCount - 1"= should > be " PatchCount". >=20 > Thanks, > Eric Agree, how about changing the logic to: if (NeedLoad) { PatchCount++; if (PatchCount > MaxPatchNumber) { ... =20 Best Regards, Hao Wu