From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.280.1578291256382001426 for ; Sun, 05 Jan 2020 22:14:16 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: hao.a.wu@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jan 2020 22:14:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,401,1571727600"; d="scan'208";a="210693230" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga007.jf.intel.com with ESMTP; 05 Jan 2020 22:14:15 -0800 Received: from fmsmsx609.amr.corp.intel.com (10.18.126.89) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 5 Jan 2020 22:14:14 -0800 Received: from fmsmsx609.amr.corp.intel.com (10.18.126.89) by fmsmsx609.amr.corp.intel.com (10.18.126.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Sun, 5 Jan 2020 22:14:13 -0800 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by fmsmsx609.amr.corp.intel.com (10.18.126.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Sun, 5 Jan 2020 22:14:13 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.197]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.39]) with mapi id 14.03.0439.000; Mon, 6 Jan 2020 14:14:12 +0800 From: "Wu, Hao A" To: "Fu, Siyuan" , "devel@edk2.groups.io" CC: "Dong, Eric" , "Ni, Ray" Subject: Re: [Patch 1/1] UefiCpuPkg: Remove redundant alignment check when calculate microcode patch size. Thread-Topic: [Patch 1/1] UefiCpuPkg: Remove redundant alignment check when calculate microcode patch size. Thread-Index: AQHVwgVrg+0i0ZF9FEGRQwivdKHLQ6fdLODg Date: Mon, 6 Jan 2020 06:14:12 +0000 Message-ID: References: <20200103071411.10760-1-siyuan.fu@intel.com> In-Reply-To: <20200103071411.10760-1-siyuan.fu@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: hao.a.wu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Fu, Siyuan > Sent: Friday, January 03, 2020 3:14 PM > To: devel@edk2.groups.io > Cc: Dong, Eric; Ni, Ray; Wu, Hao A > Subject: [Patch 1/1] UefiCpuPkg: Remove redundant alignment check when > calculate microcode patch size. >=20 > This patch removes the unnecessary alignment check on microcode patch > TotalSize > introduced by commit d786a172. The TotalSize has already been checked > with 1K > alignment and MAX_ADDRESS in previous code as below: >=20 > if ( (UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize) || > ((UINTN)MicrocodeEntryPoint + TotalSize) > MicrocodeEnd || > (DataSize & 0x3) !=3D 0 || > (TotalSize & (SIZE_1KB - 1)) !=3D 0 || > TotalSize < DataSize > ) { >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Hao A Wu > Signed-off-by: Siyuan Fu > --- > UefiCpuPkg/Library/MpInitLib/Microcode.c | 24 +++++------------------- > UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +-- > 2 files changed, 6 insertions(+), 21 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c > b/UefiCpuPkg/Library/MpInitLib/Microcode.c > index 3da5bfb9cf2f..a9d06dd4099a 100644 > --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c > +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c > @@ -1,7 +1,7 @@ > /** @file > Implementation of loading microcode on processors. >=20 > - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -397,16 +397,7 @@ LoadMicrocodePatchWorker ( > Patches[Index].Size > ); >=20 > - // > - // Zero-fill the padding area > - // Please note that AlignedSize will be no less than Size > - // > - ZeroMem ( > - Walker + Patches[Index].Size, > - Patches[Index].AlignedSize - Patches[Index].Size > - ); > - > - Walker +=3D Patches[Index].AlignedSize; > + Walker +=3D Patches[Index].Size; > } >=20 > // > @@ -578,14 +569,9 @@ LoadMicrocodePatch ( > // > // Store the information of this microcode patch > // > - if (TotalSize > ALIGN_VALUE (TotalSize, SIZE_1KB) || > - ALIGN_VALUE (TotalSize, SIZE_1KB) > MAX_UINTN - TotalLoadSize)= { > - goto OnExit; > - } > - PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) > MicrocodeEntryPoint; > - PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; > - PatchInfoBuffer[PatchCount - 1].AlignedSize =3D ALIGN_VALUE (Total= Size, > SIZE_1KB); > - TotalLoadSize +=3D PatchInfoBuffer[PatchCount - 1].AlignedSize; > + PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) > MicrocodeEntryPoint; > + PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; > + TotalLoadSize +=3D TotalSize; > } >=20 > // > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h > b/UefiCpuPkg/Library/MpInitLib/MpLib.h > index 6609c958ce8a..b6e5a1afab00 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h > @@ -1,7 +1,7 @@ > /** @file > Common header file for MP Initialize Library. >=20 > - Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -54,7 +54,6 @@ > typedef struct { > UINTN Address; > UINTN Size; > - UINTN AlignedSize; > } MICROCODE_PATCH_INFO; Thanks for the catch. Reviewed-by: Hao A Wu Best Regards, Hao Wu >=20 > // > -- > 2.19.1.windows.1