From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.1903.1580872587082279860 for ; Tue, 04 Feb 2020 19:16:27 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: hao.a.wu@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Feb 2020 19:16:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,404,1574150400"; d="scan'208";a="430026560" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga005.fm.intel.com with ESMTP; 04 Feb 2020 19:16:26 -0800 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 4 Feb 2020 19:16:26 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 4 Feb 2020 19:16:26 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.5]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.76]) with mapi id 14.03.0439.000; Wed, 5 Feb 2020 11:16:23 +0800 From: "Wu, Hao A" To: "devel@edk2.groups.io" , "Albecki, Mateusz" CC: Marcin Wojtas , "Gao, Zhichao" , "Gao, Liming" Subject: Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode Thread-Topic: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode Thread-Index: AQHV2pz2dOrHmXuuxkqK688bJ5CbXKgL6onA Date: Wed, 5 Feb 2020 03:16:23 +0000 Message-ID: References: <20200203141858.3236-1-mateusz.albecki@intel.com> <20200203141858.3236-5-mateusz.albecki@intel.com> In-Reply-To: <20200203141858.3236-5-mateusz.albecki@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: hao.a.wu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Albecki, Mateusz > Sent: Monday, February 03, 2020 10:19 PM > To: devel@edk2.groups.io > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao, Limin= g > Subject: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix PIO > transfer mode >=20 > Current driver does not support PIO transfer mode for > commands other then tuning. This change adds the code > to transfer PIO data. Hello Mateusz, Try to provide some feedbacks before I can test the patch. One test request, is it possible for you to test the asynchronous transfer= for the PIO mode? A possible method can be using an UEFI application to locate the BlockIO 2 protocol from a specific SD or eMMC device (which forced to PIO transfer m= ode). And test with the WriteBlocksEx() & ReadBlocksEx() services to see if the = RW is successful. Also, one more inline comment below: >=20 > Cc: Hao A Wu > Cc: Marcin Wojtas > Cc: Zhichao Gao > Cc: Liming Gao >=20 > Signed-off-by: Mateusz Albecki > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 3 + > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 113 > +++++++++++++++++---- > 2 files changed, 95 insertions(+), 21 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > index 15b7d12596..fd89306fab 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > @@ -157,6 +157,9 @@ typedef struct { > UINT64 Timeout; > UINT32 Retries; >=20 > + BOOLEAN PioModeTransferCompleted; > + UINT32 PioBlockIndex; > + > SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc; > SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc; > SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc; > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index 480a1664ea..43703974f7 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -1711,6 +1711,8 @@ SdMmcPrintTrb ( > DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb- > >CommandComplete)); > DEBUG ((DebugLevel, "Timeout: %d\n", Trb->Timeout)); > DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries)); > + DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", Trb- > >PioModeTransferCompleted)); > + DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex)); > DEBUG ((DebugLevel, "Adma32Desc: %X\n", Trb->Adma32Desc)); > DEBUG ((DebugLevel, "Adma64V3Desc: %X\n", Trb->Adma64V3Desc)); > DEBUG ((DebugLevel, "Adma64V4Desc: %X\n", Trb->Adma64V4Desc)); > @@ -1762,6 +1764,8 @@ SdMmcCreateTrb ( > Trb->CommandComplete =3D FALSE; > Trb->Timeout =3D Packet->Timeout; > Trb->Retries =3D SD_MMC_TRB_RETRIES; > + Trb->PioModeTransferCompleted =3D FALSE; > + Trb->PioBlockIndex =3D 0; > Trb->Private =3D Private; >=20 > if ((Packet->InTransferLength !=3D 0) && (Packet->InDataBuffer !=3D N= ULL)) { > @@ -2447,6 +2451,85 @@ SdMmcCheckCommandComplete ( > return EFI_NOT_READY; > } >=20 > +/** > + Transfers data from card using PIO method. > + > + @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA > instance. > + @param[in] Trb The pointer to the SD_MMC_HC_TRB instance. > + @param[in] IntStatus Snapshot of the normal interrupt status registe= r. > + > + @retval EFI_SUCCESS PIO transfer completed successfully. > + @retval EFI_NOT_READY PIO transfer completion still pending. > + @retval Others PIO transfer failed to complete. > +**/ > +EFI_STATUS > +SdMmcTransferDataWithPio ( > + IN SD_MMC_HC_PRIVATE_DATA *Private, > + IN SD_MMC_HC_TRB *Trb, > + IN UINT16 IntStatus > + ) > +{ > + EFI_STATUS Status; > + UINT16 Data16; > + UINT32 BlockCount; > + > + BlockCount =3D (Trb->DataLen / Trb->BlockSize); > + if (Trb->DataLen % Trb->BlockSize !=3D 0) { > + BlockCount +=3D 1; > + } > + > + if (Trb->PioBlockIndex >=3D BlockCount) { > + return EFI_SUCCESS; > + } > + > + if (Trb->Read) { > + if ((IntStatus & BIT5) =3D=3D 0) { > + return EFI_NOT_READY; > + } > + Data16 =3D BIT5; > + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16); > + > + Status =3D Private->PciIo->Mem.Read ( > + Private->PciIo, > + EfiPciIoWidthFifoUint8, > + Trb->Slot, > + SD_MMC_HC_BUF_DAT_PORT, > + Trb->BlockSize, > + (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * Trb- > >PioBlockIndex)) > + ); The read (write) process will be: 1. Wait for the Buffer Read (Write) Ready to set; 2. Clear the Buffer Read (Write) Ready bit; 3. Access the Buffer Data Port register 'Trb->BlockSize' times, each time consuming 1 byte to get all the data in a block. Since we are accessing the Buffer Data Port register, same BAR offset, so 'EfiPciIoWidthFifoUint8' is used here. Is my understanding correct? If so, I am thinking is it less efficient during the read/write of the dat= a? Since the Buffer Data Port register is 4-byte in width, data can be access= ed at most 4 bytes a time. Not sure if doing so can save time for the PIO tra= nsfer. Best Regards, Hao Wu > + if (EFI_ERROR (Status)) { > + return Status; > + } > + Trb->PioBlockIndex++; > + } else { > + if ((IntStatus & BIT4) =3D=3D 0) { > + return EFI_NOT_READY; > + } > + Data16 =3D BIT4; > + SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data16), &Data16); > + > + Status =3D Private->PciIo->Mem.Write ( > + Private->PciIo, > + EfiPciIoWidthFifoUint8, > + Trb->Slot, > + SD_MMC_HC_BUF_DAT_PORT, > + Trb->BlockSize, > + (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * Trb- > >PioBlockIndex)) > + ); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + Trb->PioBlockIndex++; > + } > + > + if (Trb->PioBlockIndex >=3D BlockCount) { > + Trb->PioModeTransferCompleted =3D TRUE; > + return EFI_SUCCESS; > + } else { > + return EFI_NOT_READY; > + } > +} > + > /** > Update the SDMA address on the SDMA buffer boundary interrupt. >=20 > @@ -2531,6 +2614,13 @@ SdMmcCheckDataTransfer ( > return Status; > } >=20 > + if (Trb->Mode =3D=3D SdMmcPioMode && !Trb->PioModeTransferCompleted) = { > + Status =3D SdMmcTransferDataWithPio (Private, Trb, IntStatus); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + } > + > if ((Trb->Mode =3D=3D SdMmcSdmaMode) && ((IntStatus & BIT3) !=3D 0)) = { > Data16 =3D BIT3; > Status =3D SdMmcHcRwMmio ( > @@ -2573,7 +2663,6 @@ SdMmcCheckTrbResult ( > EFI_STATUS Status; > EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; > UINT16 IntStatus; > - UINT32 PioLength; >=20 > Packet =3D Trb->Packet; > // > @@ -2609,26 +2698,8 @@ SdMmcCheckTrbResult ( > (Packet->SdMmcCmdBlk->CommandIndex =3D=3D > EMMC_SEND_TUNING_BLOCK)) || > ((Private->Slot[Trb->Slot].CardType =3D=3D SdCardType) && > (Packet->SdMmcCmdBlk->CommandIndex =3D=3D > SD_SEND_TUNING_BLOCK))) { > - // > - // When performing tuning procedure (Execute Tuning is set to 1) th= rough > PIO mode, > - // wait Buffer Read Ready bit of Normal Interrupt Status Register t= o be 1. > - // Refer to SD Host Controller Simplified Specification 3.0 figure = 2-29 for > details. > - // > - if ((IntStatus & BIT5) =3D=3D BIT5) { > - // > - // Clear Buffer Read Ready interrupt at first. > - // > - IntStatus =3D BIT5; > - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus); > - // > - // Read data out from Buffer Port register > - // > - for (PioLength =3D 0; PioLength < Trb->DataLen; PioLength +=3D 4)= { > - SdMmcHcRwMmio (Private->PciIo, Trb->Slot, > SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength); > - } > - Status =3D EFI_SUCCESS; > - goto Done; > - } > + Status =3D SdMmcTransferDataWithPio (Private, Trb, IntStatus); > + goto Done; > } >=20 > if (!Trb->CommandComplete) { > -- > 2.14.1.windows.1 >=20 > -------------------------------------------------------------------- >=20 > Intel Technology Poland sp. z o.o. > ul. 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