From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.505.1587360218905529751 for ; Sun, 19 Apr 2020 22:23:39 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: hao.a.wu@intel.com) IronPort-SDR: sB8cFFtMiW+Jf07Qjq2iQeS8LEXVOfa5+0qUZbMlnFXF56sH99f3JTSvXqHAEH2CLAIpe9VrTl QJKzsm2ipBXA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2020 22:23:38 -0700 IronPort-SDR: 2oJjzj0dFs7veC2IwUXKdhr6IIOsjVUxBGkTrX6wZifCE8CJ9aaGk1j0p1OxieOZff4/6l0wRo r9vVQjGHsR2A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,405,1580803200"; d="scan'208";a="333806901" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga001.jf.intel.com with ESMTP; 19 Apr 2020 22:23:37 -0700 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 19 Apr 2020 22:23:37 -0700 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 19 Apr 2020 22:23:37 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.225]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.89]) with mapi id 14.03.0439.000; Mon, 20 Apr 2020 13:23:33 +0800 From: "Wu, Hao A" To: "devel@edk2.groups.io" , "Chang, Abner (HPS SW/FW Technologist)" CC: "Chen, Gilbert" , Leif Lindholm , "Gao, Liming" Subject: Re: [edk2-devel] [PATCH v1 2/3] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch. Thread-Topic: [edk2-devel] [PATCH v1 2/3] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch. Thread-Index: AQHWDw6zF79oI2yGA0uFSUZjLxNprqiBiCgQ Date: Mon, 20 Apr 2020 05:23:33 +0000 Message-ID: References: <20200410072555.7444-1-abner.chang@hpe.com> <160466A642D4443D.7555@groups.io> In-Reply-To: <160466A642D4443D.7555@groups.io> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: hao.a.wu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Chang, Abner (HPS SW/FW Technologist) > Sent: Friday, April 10, 2020 3:26 PM > To: devel@edk2.groups.io > Cc: Chang, Abner (HPS SW/FW Technologist); Chen, Gilbert; Leif Lindholm; > Wu, Hao A; Gao, Liming > Subject: [edk2-devel] [PATCH v1 2/3] MdeModulePkg/CapsuleRuntimeDxe: > Add RISCV64 arch. >=20 > Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image. >=20 > Signed-off-by: Abner Chang > Co-authored-by: Gilbert Chen > Reviewed-by: Leif Lindholm >=20 > Cc: Hao A Wu > Cc: Liming Gao > Cc: Leif Lindholm > Cc: Gilbert Chen > --- > .../Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) >=20 > diff --git > a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf > b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf > index 942eda235c..8bf5035a69 100644 > --- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf > +++ > b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf > @@ -5,6 +5,7 @@ > # the capsule runtime services are ready. > # > # Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All r= ights > reserved.
> # SPDX-License-Identifier: BSD-2-Clause-Patent > # > ## > @@ -21,20 +22,20 @@ > # > # The following information is for reference only and not required by t= he > build tools. > # > -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 > +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 > # >=20 > [Sources] > CapsuleService.c > CapsuleService.h >=20 > -[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64] > +[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, > Sources.RISCV64] > SaveLongModeContext.c >=20 > -[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64] > +[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, > Sources.RISCV64] > CapsuleCache.c >=20 > -[Sources.Ia32, Sources.X64, Sources.EBC] > +[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64] > CapsuleReset.c Hello Abner, Sorry for the delayed response. I saw you added the new arch under sections: [Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64] [Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64] [Sources.Ia32, Sources.X64, Sources.EBC] How about the below section? It is not needed, right? [Sources.X64] Best Regards, Hao Wu >=20 > [Sources.ARM, Sources.AARCH64] > -- > 2.25.0 >=20 >=20 >=20