From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=17.151.62.68; helo=nwk-aaemail-lapp03.apple.com; envelope-from=afish@apple.com; receiver=edk2-devel@lists.01.org Received: from nwk-aaemail-lapp03.apple.com (nwk-aaemail-lapp03.apple.com [17.151.62.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CAD2C211435AE for ; Tue, 25 Sep 2018 09:25:45 -0700 (PDT) Received: from pps.filterd (nwk-aaemail-lapp03.apple.com [127.0.0.1]) by nwk-aaemail-lapp03.apple.com (8.16.0.22/8.16.0.22) with SMTP id w8PGMGXU031334; Tue, 25 Sep 2018 09:25:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apple.com; h=mime-version : content-type : sender : from : message-id : subject : date : in-reply-to : cc : to : references; s=20180706; bh=iouKAeubV/y7bqCYh2TCKEOVaEo+F8JRhliqzcEjDmA=; b=UxQT6PgyrBs/3jKGG6MJlj7d/9sQ1nbhzWTe1P/d1S5LTtdAKeUs8Skub1j9V32N7T0E Hg5DkMu9xscB0zlAR1vl15WraGLKfwOLHNcu0DUxD7wUEmZPQRVJzR8AXEvaM4EQneCq pJ5mF+GNCOjpPR1I/u/fZWFCfzklI85kSq9v7TcJULALl99u3RZ5JawRiypTUI9+e8kF WB0Z1BLzUcumgPM3oxs7oIo+CeiKJuztHxbyEq2UEQ29yd817Sx7uJjjesvljrSg44GV smbPSc5KxrbbwJsbNXrOMX9zFk3cuNF+5xu7T1PRiHxOZPooJdoCrdSqlMH2xaTKlesI Tg== Received: from ma1-mtap-s01.corp.apple.com (ma1-mtap-s01.corp.apple.com [17.40.76.5]) by nwk-aaemail-lapp03.apple.com with ESMTP id 2mnj97dkvh-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 25 Sep 2018 09:25:43 -0700 MIME-version: 1.0 Received: from nwk-mmpp-sz09.apple.com (nwk-mmpp-sz09.apple.com [17.128.115.80]) by ma1-mtap-s01.corp.apple.com (Oracle Communications Messaging Server 8.0.2.3.20180614 64bit (built Jun 14 2018)) with ESMTPS id <0PFM00BC9DMTDTD0@ma1-mtap-s01.corp.apple.com>; Tue, 25 Sep 2018 09:25:43 -0700 (PDT) Received: from process_viserion-daemon.nwk-mmpp-sz09.apple.com by nwk-mmpp-sz09.apple.com (Oracle Communications Messaging Server 8.0.2.3.20180614 64bit (built Jun 14 2018)) id <0PFM00L00CIXU900@nwk-mmpp-sz09.apple.com>; Tue, 25 Sep 2018 09:25:42 -0700 (PDT) X-Va-A: X-Va-T-CD: b3e0b1e8e2b33e7fdd733793eac878f2 X-Va-E-CD: 7cd4794eaddac4340856bee22ddd23b4 X-Va-R-CD: f2408cd09f69a7cbb3fd5a245fa1d52b X-Va-CD: 0 X-Va-ID: e3f968d2-8f94-4c4c-b5c3-b87e12d9c3bd X-V-A: X-V-T-CD: de2e0398ff672ba36d96cbf5b795659e X-V-E-CD: 7cd4794eaddac4340856bee22ddd23b4 X-V-R-CD: f2408cd09f69a7cbb3fd5a245fa1d52b X-V-CD: 0 X-V-ID: 6c1d1c49-e0ad-4126-9dec-c6867f15095f Received: from process_milters-daemon.nwk-mmpp-sz09.apple.com by nwk-mmpp-sz09.apple.com (Oracle Communications Messaging Server 8.0.2.3.20180614 64bit (built Jun 14 2018)) id <0PFM00700DGRPT00@nwk-mmpp-sz09.apple.com>; Tue, 25 Sep 2018 09:25:41 -0700 (PDT) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-09-25_10:,, signatures=0 X-Proofpoint-Scanner-Instance: nwk-grpmailp-qapp18.corp.apple.com-10000_instance1 Received: from [17.235.40.149] (unknown [17.235.40.149]) by nwk-mmpp-sz09.apple.com (Oracle Communications Messaging Server 8.0.2.3.20180614 64bit (built Jun 14 2018)) with ESMTPSA id <0PFM007TKDMACX70@nwk-mmpp-sz09.apple.com>; Tue, 25 Sep 2018 09:25:22 -0700 (PDT) Sender: afish@apple.com From: Andrew Fish Message-id: Date: Tue, 25 Sep 2018 09:25:18 -0700 In-reply-to: Cc: "Zeng, Star" , Ard Biesheuvel , "Ni, Ruiyu" , Grzegorz Jaszczyk , edk2-devel-01 , nadavh@marvell.com, fei1.wang@intel.com To: Marcin Wojtas References: <1536631417-39920-1-git-send-email-star.zeng@intel.com> <734D49CCEBEEF84792F5B80ED585239D5BE028B7@SHSMSX104.ccr.corp.intel.com> X-Mailer: Apple Mail (2.3445.6.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-25_09:, , signatures=0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: Re: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 16:25:46 -0000 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable > On Sep 25, 2018, at 8:41 AM, Marcin Wojtas wrote: >=20 > Hi Star, Ard >=20 > With this patch, my platforms which use NonDiscoverableDevices layer > for supporting generic Xhci controller, fail in a strange way: > "Synchronous Exception at 0x000000003F910AFC > PC 0x00003F910AFC (0x00003F908000+0x00008AFC) [ 0] DxeCore.dll > PC 0x00003F910AE0 (0x00003F908000+0x00008AE0) [ 0] DxeCore.dll > PC 0x00003F91BDF4 (0x00003F908000+0x00013DF4) [ 0] DxeCore.dll > PC 0x0000BF5BD000 (0x0000BF5AF000+0x0000E000) [ 1] XhciDxe.dll > PC 0xAFAFAFAFAFAFAFAF >=20 Marcin, A lot of times 0xAFAFAFAFAFAFAFAF is related to using freed memory.=20 See this PCD and its use in the DebugLib: MdePkg.dec:2168: = gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF|UINT8|0x00000008 On an X86 system 0xAFAFAFAFAFAFAFAF is a non canonical address and it = will generate a general Protection Fault exception 13 (0xD) on access.=20= Thanks, Andrew Fish > Recursive exception occurred while dumping the CPU state" >=20 > I've quickly checked and although XhcSetHsee() is eventually called > from XhcDriverBindingStart() sequence, > below line is not even executed: > XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); > The XhcDriverBindingStart() returns EFI_SUCCESS and we get the sync > abort right afterwards (haven't found exact place yet). >=20 > What makes the difference is commenting out in XhcSetHsee(): > // Status =3D PciIo->Pci.Read ( > // PciIo, > // EfiPciIoWidthUint16, > // PCI_COMMAND_OFFSET, > // sizeof (XhciCmd), > // &XhciCmd > // ); >=20 > With that everything keeps working as usual. I'd appreciate any hint. >=20 > Best regards. > Marcin >=20 > wt., 11 wrz 2018 o 04:30 Ni, Ruiyu > napisa=C5=82(a): >>=20 >> Reviewed-by: Ruiyu Ni >>=20 >> Thanks/Ray >>=20 >>> -----Original Message----- >>> From: Zeng, Star >>> Sent: Tuesday, September 11, 2018 10:04 AM >>> To: edk2-devel@lists.01.org >>> Cc: Zeng, Star ; Ni, Ruiyu = ; Wang, >>> Jian J ; Wang, Fei1 >>> Subject: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable = Bit is >>> set >>>=20 >>> When the HSEE in the USBCMD bit is a '1' and the HSE bit in the = USBSTS >>> register is a '1', the xHC shall assert out-of-band error signaling = to the host >>> and assert the SERR# pin. >>> To prevent masking any potential issues with SERR, this patch is to = set >>> USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit = is >>> set. >>>=20 >>> Cc: Ruiyu Ni >>> Cc: Jian J Wang >>> Cc: Fei1 Wang >>> Contributed-under: TianoCore Contribution Agreement 1.1 >>> Signed-off-by: Star Zeng >>> --- >>> MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 41 >>> ++++++++++++++++++++++++++++++++++ >>> 1 file changed, 41 insertions(+) >>>=20 >>> diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c >>> b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c >>> index 5f0736a516b6..89f073e1d83f 100644 >>> --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c >>> +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c >>> @@ -587,6 +587,39 @@ XhcIsSysError ( >>> } >>>=20 >>> /** >>> + Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# = Enable >>> Bit is set. >>> + >>> + The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host = Controller >>> Reset(HCRST). >>> + This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable = Bit is set. >>> + >>> + @param Xhc The XHCI Instance. >>> + >>> +**/ >>> +VOID >>> +XhcSetHsee ( >>> + IN USB_XHCI_INSTANCE *Xhc >>> + ) >>> +{ >>> + EFI_STATUS Status; >>> + EFI_PCI_IO_PROTOCOL *PciIo; >>> + UINT16 XhciCmd; >>> + >>> + PciIo =3D Xhc->PciIo; >>> + Status =3D PciIo->Pci.Read ( >>> + PciIo, >>> + EfiPciIoWidthUint16, >>> + PCI_COMMAND_OFFSET, >>> + sizeof (XhciCmd), >>> + &XhciCmd >>> + ); >>> + if (!EFI_ERROR (Status)) { >>> + if ((XhciCmd & EFI_PCI_COMMAND_SERR) !=3D 0) { >>> + XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); >>> + } >>> + } >>> +} >>> + >>> +/** >>> Reset the XHCI host controller. >>>=20 >>> @param Xhc The XHCI Instance. >>> @@ -628,6 +661,14 @@ XhcResetHC ( >>> // >>> gBS->Stall (XHC_1_MILLISECOND); >>> Status =3D XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, >>> XHC_USBCMD_RESET, FALSE, Timeout); >>> + >>> + if (!EFI_ERROR (Status)) { >>> + // >>> + // The USBCMD HSEE Bit will be reset to default 0 by USBCMD = HCRST. >>> + // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set. >>> + // >>> + XhcSetHsee (Xhc); >>> + } >>> } >>>=20 >>> return Status; >>> -- >>> 2.7.0.windows.1 >>=20 >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel =