From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=rangasai.v.chaganty@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B625222198F4C for ; Thu, 21 Dec 2017 02:26:51 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Dec 2017 02:31:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,435,1508828400"; d="scan'208";a="4572700" Received: from orsmsx106.amr.corp.intel.com ([10.22.225.133]) by orsmga008.jf.intel.com with ESMTP; 21 Dec 2017 02:31:40 -0800 Received: from orsmsx111.amr.corp.intel.com (10.22.240.12) by ORSMSX106.amr.corp.intel.com (10.22.225.133) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 21 Dec 2017 02:31:39 -0800 Received: from orsmsx110.amr.corp.intel.com ([169.254.10.149]) by ORSMSX111.amr.corp.intel.com ([10.22.240.12]) with mapi id 14.03.0319.002; Thu, 21 Dec 2017 02:31:39 -0800 From: "Chaganty, Rangasai V" To: "Yao, Jiewen" , "Zeng, Star" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTableLength & 0x3)!=0 Thread-Index: AQHTegRKSMaffeuQ/kaNJd61LFnNfaNNpCWA///1WrA= Date: Thu, 21 Dec 2017 10:31:38 +0000 Message-ID: References: <1513823692-6220-1-git-send-email-star.zeng@intel.com> <74D8A39837DF1E4DA445A8C0B3885C503AA4EEDC@shsmsx102.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503AA4EEDC@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWZhMjYxN2MtMWY3Yi00NTBmLWI5NWItNTZmMWY2MmE3ZDA2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJlZEYwSWVJOVZOcHkxRkxrdU5uSWxISkc4b0NPdkR2aDdCaWNrQWRtUHJGVVdBVmswcE9lRjU1Ykl0NW9OdjlnIn0= x-ctpclassification: CTP_IC x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Subject: Re: [PATCH] IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTableLength & 0x3)!=0 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Dec 2017 10:26:52 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: rangasai.v.chaganty@intel.com=20 -----Original Message----- From: Yao, Jiewen=20 Sent: Wednesday, December 20, 2017 7:09 PM To: Zeng, Star ; edk2-devel@lists.01.org Cc: Chaganty, Rangasai V Subject: RE: [PATCH] IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTable= Length & 0x3)!=3D0 Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Zeng, Star > Sent: Thursday, December 21, 2017 10:35 AM > To: edk2-devel@lists.01.org > Cc: Zeng, Star ; Yao, Jiewen=20 > ; Chaganty, Rangasai V=20 > > Subject: [PATCH] IntelSiliconPkg MicrocodeUpdateDxe: Fix=20 > (ExtendedTableLength & 0x3)!=3D0 >=20 > The first 48 bytes contain the microcode update header. > DataSize must be a multiple of DWORDs. > TotalSize is always a multiple of 1024. > Both size of CPU_MICROCODE_EXTENDED_TABLE_HEADER and=20 > CPU_MICROCODE_EXTENDED_TABLE are multiple of DWORDs. >=20 > So (ExtendedTableLength & 0x3)!=3D0 should be (ExtendedTableLength &=20 > 0x3)=3D=3D0. >=20 > Cc: Jiewen Yao > Cc: Rangasai V Chaganty > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c=20 > | 4 > ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git > a/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c > b/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c > index 4e8f1d5fd8a8..b99221c9696d 100644 > ---=20 > a/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c > +++ > b/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c > @@ -8,7 +8,7 @@ >=20 > MicrocodeWrite() and VerifyMicrocode() will receive untrusted input=20 > and do basic validation. >=20 > - Copyright (c) 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2017, Intel Corporation. All rights=20 > + reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of=20 > the BSD License > which accompanies this distribution. The full text of the license=20 > may be found at @@ -494,7 +494,7 @@ VerifyMicrocode ( > // > // Calculate Extended Checksum > // > - if ((ExtendedTableLength > > sizeof(CPU_MICROCODE_EXTENDED_TABLE_HEADER)) && ((ExtendedTableLength=20 > & 0x3) !=3D 0)) { > + if ((ExtendedTableLength > > sizeof(CPU_MICROCODE_EXTENDED_TABLE_HEADER)) && ((ExtendedTableLength=20 > & 0x3) =3D=3D 0)) { > CheckSum32 =3D CalculateSum32((UINT32 *)ExtendedTableHeader,=20 > ExtendedTableLength); > if (CheckSum32 =3D=3D 0) { > // > -- > 2.7.0.windows.1