From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=rangasai.v.chaganty@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B9831211BA46B for ; Thu, 31 Jan 2019 00:22:06 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Jan 2019 00:22:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,543,1539673200"; d="scan'208";a="120906082" Received: from orsmsx108.amr.corp.intel.com ([10.22.240.6]) by fmsmga008.fm.intel.com with ESMTP; 31 Jan 2019 00:22:06 -0800 Received: from orsmsx112.amr.corp.intel.com (10.22.240.13) by ORSMSX108.amr.corp.intel.com (10.22.240.6) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 31 Jan 2019 00:22:05 -0800 Received: from orsmsx108.amr.corp.intel.com ([169.254.2.237]) by ORSMSX112.amr.corp.intel.com ([169.254.3.62]) with mapi id 14.03.0415.000; Thu, 31 Jan 2019 00:22:05 -0800 From: "Chaganty, Rangasai V" To: "Solanki, Digant H" , "edk2-devel@lists.01.org" CC: "Ni, Ray" , "Gao, Liming" Thread-Topic: [PATCH 5/5] IntelSiliconPkg\Include\IndustryStandard: Update IGD_OPREGION_MBOX3 Structure Thread-Index: AQHUuTsoEUbQlLjcHU2HAOWxf7oZ0aXJCJrA Date: Thu, 31 Jan 2019 08:22:04 +0000 Message-ID: References: <20190131080109.13108-1-digant.h.solanki@intel.com> In-Reply-To: <20190131080109.13108-1-digant.h.solanki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTk3OTc2M2ItMjYxZC00ZWEzLWI2NTgtMDkxNmYwNjczNTk3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZE5leU9ISWVGQm1HbGNVdlhxcDZlcG5zZjN5VG5KU2dqTFZ3SXR1ZUN3dWRhZWo5TFIrdkZqNTZtdFI2RmpLTiJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Subject: Re: [PATCH 5/5] IntelSiliconPkg\Include\IndustryStandard: Update IGD_OPREGION_MBOX3 Structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Jan 2019 08:22:06 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chaganty, Rangasai V =20 -----Original Message----- From: Solanki, Digant H=20 Sent: Thursday, January 31, 2019 12:01 AM To: edk2-devel@lists.01.org Cc: Ni, Ray ; Gao, Liming ; Chagant= y, Rangasai V Subject: [PATCH 5/5] IntelSiliconPkg\Include\IndustryStandard: Update IGD_O= PREGION_MBOX3 Structure BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1454 Based on latest IGD OpRegion Spec, IGD_OPREGION_MBOX3 needs to be updated w= ith two new members : Physical Address of Raw VBT Data (RVDA) and Size of R= aw VBT Data (RVDS) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Digant H Solanki Cc: Ray Ni Cc: Liming Gao Cc: Rangasai V Chaganty --- IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/Intel= SiliconPkg/Include/IndustryStandard/IgdOpRegion.h index 5ce80a5be8..300a85a717 100644 --- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h +++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h @@ -4,9 +4,7 @@ =20 https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf =20 - @note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(7= 0) - - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights=20 + reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -118,7 +116,9 @@ typedef struct { UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for= IFFS feature UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer UINT32 STAT; ///< Offset 0x3B6 State Indicator - UINT8 RM31[0x46]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero. = Bug in spec 0x45(69) + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data= . Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from= Spec Version 0.90 to support VBT greater than 6KB. + UINT8 RM32[0x3A]; ///< Offset 0x3C6 - 0x3FF Reserved Must be zero. } IGD_OPREGION_MBOX3; =20 /// -- 2.18.0.windows.1