From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: rangasai.v.chaganty@intel.com) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Mon, 10 Jun 2019 17:43:23 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jun 2019 17:43:22 -0700 X-ExtLoop1: 1 Received: from orsmsx101.amr.corp.intel.com ([10.22.225.128]) by fmsmga004.fm.intel.com with ESMTP; 10 Jun 2019 17:43:22 -0700 Received: from orsmsx124.amr.corp.intel.com (10.22.240.120) by ORSMSX101.amr.corp.intel.com (10.22.225.128) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 10 Jun 2019 17:43:22 -0700 Received: from orsmsx107.amr.corp.intel.com ([169.254.1.123]) by ORSMSX124.amr.corp.intel.com ([169.254.2.18]) with mapi id 14.03.0415.000; Mon, 10 Jun 2019 17:43:21 -0700 From: "Chaganty, Rangasai V" To: "Chiu, Chasel" , "devel@edk2.groups.io" CC: "Kubacki, Michael A" , "Desimone, Nathaniel L" Subject: Re: [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI. Thread-Topic: [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI. Thread-Index: AQHVGiv+AHrpdPu5P0KXjVR1t5jOyaaVqOuA Date: Tue, 11 Jun 2019 00:43:20 +0000 Message-ID: References: <20190603164658.4668-1-chasel.chiu@intel.com> <20190603164658.4668-3-chasel.chiu@intel.com> In-Reply-To: <20190603164658.4668-3-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTAyM2JhM2EtZDRmMC00MTQwLWExMzgtNThiNzI2ZTE2OTcyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiYjhINHZadWZCZVFKSHJYTW5IYWp3TjBaMGRkZ0FHdkNVb2Q4Q0Rqdm1wakpEYm5KWlljUW9mRTh1ZnZsMGw0MyJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Return-Path: rangasai.v.chaganty@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Sai Chaganty =20 -----Original Message----- From: Chiu, Chasel=20 Sent: Monday, June 03, 2019 9:47 AM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Kubacki, Michael A ; Chaganty, Rangasai V ; Desi= mone, Nathaniel L Subject: [PATCH 2/2] KabylakeOpenBoardPkg: Support DefaultPolicyInit PPI. From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1870 Basing on FSP modes the Fsp*WrapperPeim may not have dependency on PolicyPp= i, instead it should report FSP-M or FPS-S FV to dispatcher so FSP can prod= uce DefaultPolicyInit PPIs. A PEI policy update library was created to update policy PPI basing on boar= d configuration. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiSiliconPolicyUpdateLib.c | 564 ++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++ Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc = | 50 ++++++++++++++++++++++++++++++++++++= ++++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiSiliconPolicyUpdateLib.inf | 86 ++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 700 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconP= olicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoa= rdPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..5cc7c03c61 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolic +++ yUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -0,0 +1,564 @@ +/** @file + Provides silicon policy update library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include=20 + #include #include=20 + #include #include=20 + + +/** + Get the next microcode patch pointer. + + @param[in, out] MicrocodeData - Input is a pointer to the last microcode= patch address found, + and output points to the next patch addr= ess found. + + @retval EFI_SUCCESS - Patch found. + @retval EFI_NOT_FOUND - Patch not found. +**/ +EFI_STATUS +EFIAPI +RetrieveMicrocode ( + IN OUT CPU_MICROCODE_HEADER **MicrocodeData + ) +{ + UINTN MicrocodeStart; + UINTN MicrocodeEnd; + UINTN TotalSize; + + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) =3D=3D 0) || (FixedPcdGet32= (PcdFlashMicrocodeFvSize) =3D=3D 0)) { + return EFI_NOT_FOUND; + } + + /// + /// Microcode binary in SEC + /// + MicrocodeStart =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashM= icrocodeFvBase))->HeaderLength + + sizeof (EFI_FFS_FILE_HEADER); + + MicrocodeEnd =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +=20 + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); + + if (*MicrocodeData =3D=3D NULL) { + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; =20 + } else { + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) = { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")= ); + return EFI_NOT_FOUND; + } + + TotalSize =3D (UINTN) ((*MicrocodeData)->TotalSize); + if (TotalSize =3D=3D 0) { + TotalSize =3D 2048; + } + + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + T= otalSize); + if (*MicrocodeData >=3D (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd= ) || (*MicrocodeData)->TotalSize =3D=3D (UINT32) -1) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >=3D MicrocodeEnd \n"= )); + return EFI_NOT_FOUND; + } + } + return EFI_SUCCESS; +} + +/** + Get the microcode patch pointer. + + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL i= f not found. +**/ +EFI_PHYSICAL_ADDRESS +PlatformCpuLocateMicrocodePatch ( + VOID + ) +{ + EFI_STATUS Status; + CPU_MICROCODE_HEADER *MicrocodeData; + EFI_CPUID_REGISTER Cpuid; + UINT32 UcodeRevision; + UINTN MicrocodeBufferSize; + VOID *MicrocodeBuffer =3D NULL; + + AsmCpuid ( + CPUID_VERSION_INFO, + &Cpuid.RegEax, + &Cpuid.RegEbx, + &Cpuid.RegEcx, + &Cpuid.RegEdx + ); + + UcodeRevision =3D GetCpuUcodeRevision (); MicrocodeData =3D NULL; whil= e=20 + (TRUE) { + /// + /// Find the next patch address + /// + Status =3D RetrieveMicrocode (&MicrocodeData); + DEBUG ((DEBUG_INFO, "MicrocodeData =3D %x\n", MicrocodeData)); + + if (Status !=3D EFI_SUCCESS) { + break; + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision= )) { + break; + } + } + + if (EFI_ERROR (Status)) { + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; } + + /// + /// Check that microcode patch size is <=3D 128K max size, /// then=20 + copy the patch from FV to temp buffer for faster access. + /// + MicrocodeBufferSize =3D (UINTN) MicrocodeData->TotalSize; + + if (MicrocodeBufferSize <=3D MAX_MICROCODE_PATCH_SIZE) { + MicrocodeBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferS= ize)); + if (MicrocodeBuffer !=3D NULL) { + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); + + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; + } else { + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode= Patch.\n")); + } + } else { + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max=20 +allowed size of 128K.\n")); + } + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; } + +/** + Update HSIO policy per board. + + @param[in] Policy - Policy PPI pointer (caller should ensure it is=20 + valid pointer) + +**/ +VOID +InstallPlatformHsioPtssTable ( + IN VOID *Policy + ) +{ + HSIO_PTSS_TABLES *UnknowPtssTables; + HSIO_PTSS_TABLES *SpecificPtssTables; + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 UnknowTableSize; + UINT32 SpecificTableSize; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + EFI_STATUS Status; + + Status =3D GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *)= =20 + &HsioPciePreMemConfig); ASSERT_EFI_ERROR (Status); Status =3D=20 + GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *)=20 + &HsioSataPreMemConfig); ASSERT_EFI_ERROR (Status); + + UnknowPtssTables =3D NULL; + UnknowTableSize =3D 0; + SpecificPtssTables =3D NULL; + SpecificTableSize =3D 0; + + if (GetPchGeneration () =3D=3D SklPch) { + switch (PchStepping ()) { + case PchLpB0: + case PchLpB1: + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPts= sTable1); + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable1Size); + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsi= oPtssTable1); + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable1Size); + break; + case PchLpC0: + case PchLpC1: + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPts= sTable2); + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable2Size); + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsi= oPtssTable2); + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable2Size); + break; + case PchHB0: + case PchHC0: + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table1); + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable1Size); + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable1); + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable1Size); + break; + case PchHD0: + case PchHD1: + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table2); + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable2); + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables =3D NULL; + UnknowTableSize =3D 0; + SpecificPtssTables =3D NULL; + SpecificTableSize =3D 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } else { + switch (PchStepping ()) { + case KblPchHA0: + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table2); + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable2); + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables =3D NULL; + UnknowTableSize =3D 0; + SpecificPtssTables =3D NULL; + SpecificTableSize =3D 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } + + PtssTableIndex =3D 0; + MaxSataPorts =3D GetPchMaxSataPortNum (); MaxPciePorts =3D=20 + GetPchMaxPciePortNum (); ZeroMem (PcieTopologyReal, sizeof=20 + (PcieTopologyReal)); // //Populate PCIe topology based on lane=20 + configuration // for (PciePort =3D 0; PciePort < MaxPciePorts;=20 + PciePort +=3D 4) { + Status =3D GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); + ASSERT_EFI_ERROR (Status); + + RpBase =3D MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (= UINT32) RpFunction); + StrapFuseCfg =3D MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg =3D (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_= RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value =3D %d\n",=20 + PciePort, PcieControllerCfg)); } for (Index =3D 0; Index <=20 + MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology =3D %d\n",=20 + Index, PcieTopologyReal[Index])); } // //Case 1: BoardId is known,=20 + Topology is known/unknown //Case 1a: SATA // PtssTables =3D=20 + SpecificPtssTables; TableSize =3D SpecificTableSize; for (Index =3D 0;= =20 + Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_SATA) + ) + { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_HS= IO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_R= X_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD= 20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnab= le =3D TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry]= .PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _PCH_HSIO_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWORD= 8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp= Enable =3D TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp= =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSI= O_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWORD= 8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp= Enable =3D TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp= =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSI= O_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 1b: PCIe + // + for (Index =3D 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_PCIEDMI) && + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_HS= IO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_R= X_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD25_= CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = =3D TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Ent= ry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + + } else { + ASSERT (FALSE); + } + } + } + } + } + // + //Case 2: BoardId is unknown, Topology is known/unknown // if=20 + (PtssTableIndex =3D=3D 0) { + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be=20 + applied\n")); + + PtssTables =3D UnknowPtssTables; + TableSize =3D UnknowTableSize; + + for (Index =3D 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LA= NE_OWN_SATA) + ) + { + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_= HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO= _RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWO= RD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEn= able =3D TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry= ].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + + } else if (PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) = R_PCH_HSIO_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE00MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleA= mpEnable =3D TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleA= mp =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_H= SIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0)= ; + + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE01MARGIN_5_0) { + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleA= mpEnable =3D TRUE; + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleA= mp =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_H= SIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0)= ; + } + } else { + ASSERT (FALSE); + } + } + } + } + } + for (Index =3D 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { + for (Entry =3D 0; Entry < TableSize; Entry++) { + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LA= NE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology))= { + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_= HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO= _RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD2= 5_CTLE_ADAPT_OFFSET_CFG_4_0)) { + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = =3D TRUE; + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[E= ntry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0= ); + } else { + ASSERT (FALSE); + } + } + } + } + } + } +} + +/** + Update PreMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + VOID *Buffer; + UINT8 SpdAddressTable[4]; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); + + if (Policy !=3D NULL) { + SpdAddressTable[0] =3D PcdGet8 (PcdMrcSpdAddressTable0); + SpdAddressTable[1] =3D PcdGet8 (PcdMrcSpdAddressTable1); + SpdAddressTable[2] =3D PcdGet8 (PcdMrcSpdAddressTable2); + SpdAddressTable[3] =3D PcdGet8 (PcdMrcSpdAddressTable3); + + MiscPeiPreMemConfig =3D NULL; + Status =3D GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID = *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + if (MiscPeiPreMemConfig !=3D NULL) { + // + // Pass board specific SpdAddressTable to policy + // + CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) Spd= AddressTable, (sizeof (UINT8) * 4)); + } + MemConfigNoCrc =3D NULL; + Status =3D GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &= MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + + if (MemConfigNoCrc !=3D NULL) { + MemConfigNoCrc->PlatformMemorySize =3D PcdGet32=20 + (PcdPeiMinMemorySize); + + // + // Only if SpdAddressTables are all zero we need to pass hard-coded = SPD data buffer. + // Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTab= les policy. + // + if (*((UINT32 *) (UINTN) SpdAddressTable) =3D=3D 0) { + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n")); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(= UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(= UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Sett= ings...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer,= 12); + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*= ) Buffer + 12, 12); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffe= r, 8); + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT= 8*) Buffer + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rc= omp Target Settings...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), = Buffer, 6); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Bu= ffer, 10); + } + } + // + // Update PCD policy + // + InstallPlatformHsioPtssTable (Policy); } + + return Policy; +} + +/** + Update PostMem phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + GRAPHICS_PEI_CONFIG *GtConfig; + CPU_CONFIG *CpuConfig; + + DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); + + GtConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid,=20 + (VOID *)&GtConfig); ASSERT_EFI_ERROR (Status); + + if (GtConfig !=3D NULL) { + // + // Always enable PEI graphics initialization. + // + GtConfig->PeiGraphicsPeimInit =3D 1; + Size =3D 0; + Buffer =3D NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->GraphicsConfigPtr =3D MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + GtConfig->GraphicsConfigPtr =3D 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", G= tConfig->GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size= )); + Size =3D 0; + Buffer =3D NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, = &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->LogoPtr =3D MemBuffer; + GtConfig->LogoSize =3D Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + GtConfig->LogoPtr =3D 0; + GtConfig->LogoSize =3D 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtCon= fig->LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n",=20 + GtConfig->LogoSize)); } + + CpuConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID=20 + *)&CpuConfig); ASSERT_EFI_ERROR (Status); + + if (CpuConfig !=3D NULL) { + CpuConfig->MicrocodePatchAddress =3D PlatformCpuLocateMicrocodePatch=20 +(); + } + return Policy; +} + +/** + Update late phase silicon policy per board. + + @param[in] Policy - Policy PPI pointer. + + @retval Policy - Policy PPI pointer. + +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..1b0611e57a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -233,6 +233,12 @@ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf !endif } + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper upda= ting UPD. + # Add policy as dependency for FSP Wrapper + # IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf @@ -244,6 +250,26 @@ # NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyNoti= fyLib/PeiPreMemSiliconPolicyNotifyLib.inf } +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-M=20 +dispatched. (only PrePolicy silicon-init executed) + # Do not add policy dependency and let FspmWrapper report FSP-M FV to di= spatcher. + # + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { + + =20 +SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyI +nitLibNull/SiliconPolicyInitLibNull.inf + } + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP t= o install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch=20 +mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibi= lity. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { + + =20 +SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyIni +tLib/PeiPreMemSiliconPolicyInitLib.inf + } +!endif + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE @@ -253,1= 1 +279,35 @@ !endif } =20 +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # In FSP API mode the policy has to be installed before FSP Wrapper upda= ting UPD. + # Add policy as dependency for FSP Wrapper + # IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf } $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf +!else + # + # In FSP Dispatch mode the policy will be installed after FSP-S=20 +dispatched. (only PrePolicy silicon-init executed) + # Do not add policy dependency and let FspsWrapper report FSP-S FV to di= spatcher. + # + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { + + =20 +SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyI +nitLibNull/SiliconPolicyInitLibNull.inf + } + # + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP t= o install a default policy PPI. + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch=20 +mode can generate different policy structure + # for different FSP revisions, but they must maintain backward compatibi= lity. + # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf { + + =20 +SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyIni +tLib/PeiPostMemSiliconPolicyInitLib.inf + } +!endif =20 # # Security diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconP= olicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenB= oardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.= inf new file mode 100644 index 0000000000..aa163ebf08 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/PeiSiliconPolic +++ yUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -0,0 +1,86 @@ +### @file +# Component information file for silicon policy update library # #=20 +Copyright (c) 2019, Intel Corporation. All rights reserved.
# #=20 +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSiliconPolicyUpdateLib + FILE_GUID =3D 14F5D83D-76A5-4241-BEC5-987E70E233D5 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + ConfigBlockLib + BaseMemoryLib + MemoryAllocationLib + PeiLib + CpuPlatformLib + PchPcieRpLib + PchInfoLib + MmPciLib + IoLib + PchHsioLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiSiliconPolicyUpdateLib.c + +[Guids] + gMemoryConfigNoCrcGuid + gTianoLogoGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 -- 2.13.3.windows.1