From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.2546.1571376573360501483 for ; Thu, 17 Oct 2019 22:29:33 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: rangasai.v.chaganty@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Oct 2019 22:29:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,310,1566889200"; d="scan'208";a="199602829" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2019 22:29:32 -0700 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 17 Oct 2019 22:29:32 -0700 Received: from fmsmsx104.amr.corp.intel.com ([169.254.3.133]) by fmsmsx116.amr.corp.intel.com ([169.254.2.25]) with mapi id 14.03.0439.000; Thu, 17 Oct 2019 22:29:31 -0700 From: "Chaganty, Rangasai V" To: "Wang, Iwen Evelyn" , "devel@edk2.groups.io" CC: "Huang, Jenny" , "Shih, More" , "Ni, Ray" , "Yao, Jiewen" Subject: Re: [v9 v9] IntelSiliconPkg-Vtd: A new PMR interface Thread-Topic: [v9 v9] IntelSiliconPkg-Vtd: A new PMR interface Thread-Index: AQHVhVJwjcOXP3N+gUOXlpif2Ze5Ladf3ufQ Date: Fri, 18 Oct 2019 05:29:31 +0000 Message-ID: References: <20191018012139.15304-1-iwen.evelyn.wang@intel.com> In-Reply-To: <20191018012139.15304-1-iwen.evelyn.wang@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTg4MzFkNDQtYjE0OS00YzQ2LTkwYTctNzMzOWMzZjdkMTZhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoibFFmZnhcL0ltWjRDZExrXC92aTg4SmxTeXRYM2szR1hhNWtcL2ZFTjRDb0dcL3hBc0Q1b0tCaFBUNDhxa2NIM1wvaUNrIn0= x-ctpclassification: CTP_NT x-originating-ip: [10.1.200.108] MIME-Version: 1.0 Return-Path: rangasai.v.chaganty@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Sai Chaganty -----Original Message----- From: Wang, Iwen Evelyn=20 Sent: Thursday, October 17, 2019 6:22 PM To: devel@edk2.groups.io Cc: Huang, Jenny ; Shih, More ;= Ni, Ray ; Chaganty, Rangasai V ; Yao, Jiewen Subject: [v9 v9] IntelSiliconPkg-Vtd: A new PMR interface REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1770 1) IOMMU PMR feature should be generic to support different hardware archit= ecture. Platforms may request no overlap between PMR regions and system res= erve memory. Create an interface to publish PLMR/PHMR regions. It allows si= licon code to adjust PLMR/PHMR region base on the project needs. 2) A new GetVtdPmrAlignmentLib for silicon code to get PMR alignment values= . Signed-off-by: Evelyn Wang Cc: Jenny Huang Cc: More Shih Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jiewen Yao --- In V2: 1) Fixed the EFIAPI is missing in library API issue 2) Logs will be provided to make sure the backwards compatibility 3) Replaced BIT0 with EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL 4) Renamed GetVtdPmrAlignmentLib to PeiGetVtdPmrAlignmentLib 5) Fixed the indent in IntelVTdPmrPei.c 6) Follow VTd spec to define the data type of the SYSTEM_MEM_INFO_HOB Applied few changes coordinately --- In V3: 1) Fixed the EFIAPI is missing in library API issue 2) Fixed the S3 resume assert --- In V4: Fixed the missing EFIAPI in .h file and added few more comments --- In V5: In order to align with the future planning, changed the hob name from SYSTE= M_MEM_INFO_HOB to VTD_PMR_INFO_HOB --- In V6: 1) Revised comments 2) Moved VtdPmrInfoHob.h under Guid folder 3) Separated to few commits --- In V7: 1) Only the functions declared in library header file should have EFIAPI 2) Added a few comments to avoid confusion 3) Fixed a case error --- In V8: 1) Fixed a typo and commit message --- In V9: 1) Fixed a typo and articles --- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c = | 4 ++-- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c = | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++----------------------- Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPm= rAlignmentLib.c | 164 +++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.in= f | 5 ++++- Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h = | 29 +++++++++++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.h = | 22 ++++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec = | 11 +++++++++-- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc = | 3 ++- Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPm= rAlignmentLib.inf | 32 ++++++++++++++++++++++++++++++++ 9 files changed, 325 insertions(+), 29 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmr.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVT= dPmr.c index 37283f0fab..9103e53922 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.= c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdP +++ mr.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 + reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -294,7 +294,7 @@ SetDmaProtectedRange ( UINTN Index; EFI_STATUS Status; =20 - DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] [0x%lx, = 0x%lx]\n", EngineMask, LowMemoryBase, LowMemoryLength, HighMemoryBase, High= MemoryLength)); + DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x]=20 + [0x%016lx, 0x%016lx]\n", EngineMask, LowMemoryBase, LowMemoryLength,=20 + HighMemoryBase, HighMemoryLength)); =20 for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { diff --git a/Silico= n/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c b/Silic= on/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c index ca099ed71d..ea944aa40c 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdP +++ mrPei.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 + reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -20,7 +20,7 @@ #include #include #include - +#include #include "IntelVTdPmrPei.h" =20 EFI_GUID mVTdInfoGuid =3D { @@ -424,37 +424,79 @@ InitDmaProtection ( UINTN MemoryAlignment; UINTN LowBottom; UINTN LowTop; - UINTN HighBottom; + UINT64 HighBottom; UINT64 HighTop; DMA_BUFFER_INFO *DmaBufferInfo; VOID *Hob; EFI_PEI_PPI_DESCRIPTOR *OldDescriptor; EDKII_IOMMU_PPI *OldIoMmuPpi; + VTD_PMR_INFO_HOB *VtdPmrHob; + VOID *VtdPmrHobPtr; =20 + // + // Initialization + // + VtdPmrHob =3D NULL; Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); + VtdPmrHobPtr =3D GetFirstGuidHob (&gVtdPmrInfoDataHobGuid); + + /** + When gVtdPmrInfoDataHobGuid exists, it means: + 1. Dma buffer is reserved by memory initialize code + 2. PeiGetVtdPmrAlignmentLib is used to get alignment + 3. PMR regions are determined by the system memory map + 4. PMR regions will be conveyed through VTD_PMR_INFO_HOB + + When gVtdPmrInfoDataHobGuid dosen't exist, it means: + 1. IntelVTdPmr driver will calcuate the PMR memory alignment + 2. Dma buffer is reserved by AllocateAlignedPages() **/ if=20 + (VtdPmrHobPtr =3D=3D NULL) { + // + // Calcuate the PMR memory alignment + // + DEBUG ((DEBUG_INFO, "No special requirements for PMR memory\n")); + LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo->Engine= Mask); + HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo->Engi= neMask); + if (LowMemoryAlignment < HighMemoryAlignment) { + MemoryAlignment =3D (UINTN)HighMemoryAlignment; + } else { + MemoryAlignment =3D LowMemoryAlignment; + } + ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D=20 + ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment)); =20 - DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferS= ize)); + // + // Allocate memory for DMA buffer + // + DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SIZE= _TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); + ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); + if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { + DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); + return EFI_OUT_OF_RESOURCES; + } =20 - LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo->EngineMa= sk); - HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo->Engine= Mask); - if (LowMemoryAlignment < HighMemoryAlignment) { - MemoryAlignment =3D (UINTN)HighMemoryAlignment; + LowBottom =3D 0; + LowTop =3D DmaBufferInfo->DmaBufferBase; + HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBuffer= Size; + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); } else { - MemoryAlignment =3D LowMemoryAlignment; - } - ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D ALIGN_VALUE(DmaBufferInfo->D= maBufferSize, MemoryAlignment)); - DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SIZE_T= O_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); - ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); - if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { - DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); - return EFI_OUT_OF_RESOURCES; - } =20 - DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", DmaBufferInfo->DmaBufferB= ase)); + // + // Get the PMR ranges information for the VTd PMR hob + // + VtdPmrHob =3D GET_GUID_HOB_DATA (VtdPmrHobPtr); + DmaBufferInfo->DmaBufferBase =3D VtdPmrHob->ProtectedLowLimit; + LowBottom =3D VtdPmrHob->ProtectedLowBase; + LowTop =3D VtdPmrHob->ProtectedLowLimit; + HighBottom =3D VtdPmrHob->ProtectedHighBase; + HighTop =3D VtdPmrHob->ProtectedHighLimit; } =20 DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase + Dm= aBufferInfo->DmaBufferSize; DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo->DmaBufferBase; + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n",=20 + DmaBufferInfo->DmaBufferSize)); DEBUG ((DEBUG_INFO, " DmaBufferBase :=20 + 0x%x\n", DmaBufferInfo->DmaBufferBase)); =20 // // (Re)Install PPI. @@ -472,10 +514,6 @@ InitDmaProtection ( } ASSERT_EFI_ERROR (Status); =20 - LowBottom =3D 0; - LowTop =3D DmaBufferInfo->DmaBufferBase; - HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSi= ze; - HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); =20 Status =3D SetDmaProtectedRange ( VTdInfo, @@ -559,7 +597,7 @@ InitVTdPmrForAll ( VTD_INFO *VTdInfo; UINTN LowBottom; UINTN LowTop; - UINTN HighBottom; + UINT64 HighBottom; UINT64 HighTop; =20 Hob =3D GetFirstGuidHob (&mVTdInfoGuid); diff --git a/Silicon/Intel/Inte= lSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.c b/S= ilicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrA= lignmentLib.c new file mode 100644 index 0000000000..5f63c857d6 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/Pei +++ GetVtdPmrAlignmentLib.c @@ -0,0 +1,164 @@ +/** @file + Library to get Global VTd PMR alignment information. + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef union { + struct { + UINT32 Low; + UINT32 High; + } Data32; + UINT64 Data; +} UINT64_STRUCT; + +/** + Get the protected low memory alignment. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected low memory alignment. Ex: 0x100000 **/ +UINT32 +GetGlobalVTdPlmrAlignment ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Data32; + + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0xFFFFFFFF); + Data32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG); + Data32 =3D ~Data32 + 1; + + return Data32; +} + +/** + Get the protected high memory alignment. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected high memory alignment. Ex: 0x100000 **/=20 +UINT64_STRUCT GetGlobalVTdPhmrAlignment ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress + ) +{ + UINT64_STRUCT Data64; + + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG,=20 + 0xFFFFFFFFFFFFFFFF); Data64.Data =3D MmioRead64 (VtdUnitBaseAddress +=20 + R_PMEN_HIGH_BASE_REG); Data64.Data =3D ~Data64.Data + 1; Data64.Data = =3D=20 + Data64.Data & (LShiftU64 (1, HostAddressWidth) - 1); + + return Data64; +} + +/** + Get the global VT-d protected memory alignment. + @return The maximum protected memory alignment. Ex: 0x100000 **/=20 +UINTN EFIAPI GetGlobalVtdPmrAlignment ( +) +{ + UINT32 LowMemoryAlignment; + UINT64_STRUCT HighMemoryAlignment; + UINTN MemoryAlignment; + UINT32 GlobalVTdBaseAddress; + EFI_STATUS Status; + UINTN VtdIndex; + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + EFI_ACPI_DMAR_DRHD_HEADER *DrhdHeader; + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; + + // + // Initialization + // + GlobalVTdBaseAddress =3D 0xFFFFFFFF; + LowMemoryAlignment =3D 0; + HighMemoryAlignment.Data =3D 0; + MemoryAlignment =3D 0; + Status =3D EFI_UNSUPPORTED; + VtdIndex =3D 0; + DmarHeader =3D NULL; + DrhdHeader =3D NULL; + AcpiDmarTable =3D NULL; + + // + // Fetch the PEI DMAR ACPI Table that created and installed in=20 + PlatformVTdInfoSamplePei.c // Status =3D PeiServicesLocatePpi ( + &gEdkiiVTdInfoPpiGuid, + 0, + NULL, + (VOID **)&AcpiDmarTable + ); + if (EFI_ERROR (Status)) { + + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi gEdkiiVTdInfoPpiGuid failed= \n")); + Status =3D EFI_NOT_FOUND; + MemoryAlignment =3D SIZE_1MB; + + } else { + + // + // Seatch the DRHD structure with INCLUDE_PCI_ALL flag Set -> Global V= T-d + // + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTabl= e + 1)); + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Heade= r.Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + DrhdHeader =3D (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader; + if ((DrhdHeader->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL)= =3D=3D EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) { + GlobalVTdBaseAddress =3D (UINT32)DrhdHeader->RegisterBaseAddress= ; + DEBUG ((DEBUG_INFO," GlobalVTdBaseAddress: %x\n", GlobalVTdBase= Address)); + } + VtdIndex++; + + break; + + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader = + DmarHeader->Length); + } + + if (GlobalVTdBaseAddress =3D=3D 0xFFFFFFFF) { + + DEBUG ((DEBUG_ERROR, "Error! Please set INCLUDE_PCI_ALL flag to your= Global VT-d\n")); + MemoryAlignment =3D SIZE_1MB; + + } else { + // + // Get the alignment information from VT-d register + // + LowMemoryAlignment =3D GetGlobalVTdPlmrAlignment (AcpiDmarTable->Hos= tAddressWidth, GlobalVTdBaseAddress); + HighMemoryAlignment =3D GetGlobalVTdPhmrAlignment (AcpiDmarTable->Ho= stAddressWidth, GlobalVTdBaseAddress); + if (LowMemoryAlignment < HighMemoryAlignment.Data) { + MemoryAlignment =3D (UINTN)HighMemoryAlignment.Data; + } else { + MemoryAlignment =3D LowMemoryAlignment; + } + } + } + + return MemoryAlignment; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmrPei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/In= telVTdPmrPei.inf index 39b914cd00..3eb2b510ca 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdP +++ mrPei.inf @@ -4,7 +4,7 @@ # This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI # and = provide DMA protection in PEI. # -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -40,6 +40,9 @@ IoLib CacheMaintenanceLib =20 +[Guids] + gVtdPmrInfoDataHobGuid ## CONSUMES + [Ppis] gEdkiiIoMmuPpiGuid ## PRODUCES gEdkiiVTdInfoPpiGuid ## CONSUMES diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h b/S= ilicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h new file mode 100644 index 0000000000..d08b9818e3 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h @@ -0,0 +1,29 @@ +/** @file + The definition for VTD PMR Regions Information Hob. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + + +#ifndef _VTD_PMR_INFO_HOB_H_ +#define _VTD_PMR_INFO_HOB_H_ + +/// +/// This interface is to report the PMR regions information /// PMR=20 +regions means PLMR/PHMR base and limit /// When gVtdPmrInfoDataHobGuid=20 +exists, it means: +/// 1. Dma buffer is reserved by memory initialize code /// 2.=20 +PeiGetVtdPmrAlignmentLib is used to get alignment /// 3. PMR regions=20 +are determined by the system memory map /// 4. PMR regions will be=20 +conveyed through VTD_PMR_INFO_HOB /// typedef struct { + UINT32 ProtectedLowBase; //PLMR Base + UINT32 ProtectedLowLimit; //PLMR Limit + UINT64 ProtectedHighBase; //PHMR Base + UINT64 ProtectedHighLimit; //PHMR Limit +} VTD_PMR_INFO_HOB; + +#endif // _VTD_PMR_INFO_HOB_H_ + diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlig= nmentLib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlig= nmentLib.h new file mode 100644 index 0000000000..ebfe904053 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmen +++ tLib.h @@ -0,0 +1,22 @@ +/** @file + Get the global VTd PMR alignment information library. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __GET_VTD_PMR_ALIGN_LIB_H__ +#define __GET_VTD_PMR_ALIGN_LIB_H__ +#include + +/** + Get the global VT-d protected memory alignment. + @return The maximum protected memory alignment. Ex: 0x100000 **/ + +UINTN +EFIAPI +GetGlobalVtdPmrAlignment ( +); + +#endif // __GET_VTD_PMR_ALIGN_LIB_H__ diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index fe5bfa0dc6..5e8082e113 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -3,7 +3,7 @@ # # This package provides common open source Intel silicon modules. # -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2019, Intel Corporation. All rights=20 +reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -18,10 +18,14 @@ Include =20 [LibraryClasses.IA32, LibraryClasses.X64] - ## @libraryclass Provides services to access Microcode region on flash = device. + ## @libraryclass Provides services to access Microcode region on flash d= evice. # MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h =20 + ## @libraryclass Provides services to access VTd PMR information # =20 + PeiGetVtdPmrAlignmentLib|Include/Library/PeiGetVtdPmrAlignmentLib.h + [Guids] ## GUID for Package token space # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735} @@ -35,6 +39,9 @@ ## Include/Guid/MicrocodeFmp.h gMicrocodeFmpImageTypeIdGuid =3D { 0x96d4fdcd, 0x1502, 0x424d, { 0x= 9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } } =20 + ## HOB GUID to get memory information after MRC is done. The hob data=20 + will be used to set the PMR ranges gVtdPmrInfoDataHobGuid =3D=20 + {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e,=20 + 0xe7, 0xe7 } } + [Ppis] gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } =20 diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dsc index 58b5b656ef..352d1e2b6d 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -1,7 +1,7 @@ ## @file # This package provides common open source Intel silicon modules. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -34,6 +34,7 @@ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/Microcod= eFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf + =20 + PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignment + Lib/PeiGetVtdPmrAlignmentLib.inf =20 [LibraryClasses.common.PEIM] PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf diff --git a/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib= /PeiGetVtdPmrAlignmentLib.inf b/Silicon/Intel/IntelSiliconPkg/Library/PeiGe= tVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.inf new file mode 100644 index 0000000000..ebb2cc2a7f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/Pei +++ GetVtdPmrAlignmentLib.inf @@ -0,0 +1,32 @@ +## @file +# Component INF file for the GetVtdPmrAlignment library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# #=20 +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiGetVtdPmrAlignmentLib +FILE_GUID =3D 0332BE93-0547-4D87-A7FA-0D9D76C53187 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PeiGetVtdPmrAlignmentLib + +[Packages] +MdePkg/MdePkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] +PeiGetVtdPmrAlignmentLib.c + +[LibraryClasses] +DebugLib +BaseMemoryLib +MemoryAllocationLib +BaseLib +PeiServicesLib + +[Ppis] +gEdkiiVTdInfoPpiGuid ## CONSUMES -- 2.16.2.windows.1