From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.13991.1573070421615086034 for ; Wed, 06 Nov 2019 12:00:21 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: rangasai.v.chaganty@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2019 12:00:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,275,1569308400"; d="scan'208";a="201194368" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga007.fm.intel.com with ESMTP; 06 Nov 2019 12:00:21 -0800 Received: from fmsmsx119.amr.corp.intel.com (10.18.124.207) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 6 Nov 2019 12:00:21 -0800 Received: from fmsmsx104.amr.corp.intel.com ([169.254.3.133]) by FMSMSX119.amr.corp.intel.com ([169.254.14.173]) with mapi id 14.03.0439.000; Wed, 6 Nov 2019 12:00:20 -0800 From: "Chaganty, Rangasai V" To: "Yao, Jiewen" , "devel@edk2.groups.io" CC: "Ni, Ray" , "Lou, Yun" Subject: Re: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Topic: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Index: AQHVj+cpS3zlf7NEKU+zkxkm4yjEwqd+l7Lw Date: Wed, 6 Nov 2019 20:00:19 +0000 Message-ID: References: <20191031123127.10900-1-jiewen.yao@intel.com> <20191031123127.10900-2-jiewen.yao@intel.com> In-Reply-To: <20191031123127.10900-2-jiewen.yao@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjgwNzgwNmMtMTIwNC00ZDM5LWEwODEtNzdiMmJhODZmYTg4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiWU1OdkpRUXJ5NkFRRnRpT3R4dGlRZnNUV0ZGUEVsdVZJRTJcL0dlWXpPUW9jS2ZPb2FwbGluUjIzMTFtT2NXcG8ifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.1.200.108] MIME-Version: 1.0 Return-Path: rangasai.v.chaganty@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Jiewen,=20 Few comments: 1. Can we put a reference to the spec at the file header? 2. Can we group all the macros at the top followed by structure definitions= ? 3. Is it possible to add some high level description above the structure de= finition that describes the structure? 4. I see line 80 is commented out. Can we remove that line? 5. Please add some description about the change after line 5. Thanks, Sai -----Original Message----- From: Yao, Jiewen=20 Sent: Thursday, October 31, 2019 5:31 AM To: devel@edk2.groups.io Cc: Ni, Ray ; Chaganty, Rangasai V ; Lou, Yun Subject: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity defi= nition. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2303 Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Yun Lou Signed-off-by: Jiewen Yao --- Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h = | 66 ++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPc= iSecurity.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelP= ciSecurity.h new file mode 100644 index 0000000000..a8c5483165 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecuri= ty.h @@ -0,0 +1,66 @@ +/** @file + Intel PCI security data structure + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __INTEL_PCI_SECURITY_H__ +#define __INTEL_PCI_SECURITY_H__ + +#pragma pack(1) + +typedef struct { + UINT16 CapId; // 0x23: DVSEC + UINT16 CapVersion:4; // 1 + UINT16 NextOffset:12; + UINT16 DvSecVendorId; // 0x8086 + UINT16 DvSecRevision:4; // 1 + UINT16 DvSecLength:12; + UINT16 DvSecId; // 0x3E: Measure +} INTEL_PCI_DIGEST_CAPABILITY_HEADER; + +#define INTEL_PCI_CAPID_DVSEC 0x23 +#define INTEL_PCI_DVSEC_VENDORID_INTEL 0x8086 +#define INTEL_PCI_DVSEC_DVSECID_MEASUREMENT 0x3E + +typedef union { + struct { + UINT8 DigestModified:1; // RW1C + UINT8 Reserved0:7; + } Bits; + UINT8 Data; +} INTEL_PCI_DIGEST_DATA_MODIFIED; + +#define INTEL_PCI_DIGEST_MODIFIED BIT0 + +typedef union { + struct { + UINT8 Digest0Valid:1; // RO + UINT8 Digest0Locked:1; // RO + UINT8 Digest1Valid:1; // RO + UINT8 Digest1Locked:1; // RO + UINT8 Reserved1:4; + } Bits; + UINT8 Data; +} INTEL_PCI_DIGEST_DATA_VALID; + +#define INTEL_PCI_DIGEST_0_VALID BIT0 +#define INTEL_PCI_DIGEST_0_LOCKED BIT1 +#define INTEL_PCI_DIGEST_1_VALID BIT2 +#define INTEL_PCI_DIGEST_1_LOCKED BIT3 + +typedef struct { + INTEL_PCI_DIGEST_DATA_MODIFIED Modified; // RW1C + INTEL_PCI_DIGEST_DATA_VALID Valid; // RO + UINT16 TcgAlgId; // RO + UINT8 FirmwareID; // RO + UINT8 Reserved; +//UINT8 Digest[]; +} INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE; + +#pragma pack() + +#endif + --=20 2.19.2.windows.1