From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.10092.1574104452987226103 for ; Mon, 18 Nov 2019 11:14:13 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: rangasai.v.chaganty@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Nov 2019 11:14:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,321,1569308400"; d="scan'208";a="289353850" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga001.jf.intel.com with ESMTP; 18 Nov 2019 11:14:12 -0800 Received: from fmsmsx104.amr.corp.intel.com ([169.254.3.245]) by FMSMSX106.amr.corp.intel.com ([169.254.5.77]) with mapi id 14.03.0439.000; Mon, 18 Nov 2019 11:14:11 -0800 From: "Chaganty, Rangasai V" To: "Desimone, Nathaniel L" , "devel@edk2.groups.io" CC: "Chiu, Chasel" , "Kubacki, Michael A" Subject: Re: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Thread-Topic: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Thread-Index: AQHVmrPqSzd/4LNMGkuTECDcR4cvX6eRUnXw Date: Mon, 18 Nov 2019 19:14:11 +0000 Message-ID: References: <20191114060655.5161-1-nathaniel.l.desimone@intel.com> <20191114060655.5161-6-nathaniel.l.desimone@intel.com> In-Reply-To: <20191114060655.5161-6-nathaniel.l.desimone@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODIwZGZjNGMtMTRmNC00YjRkLTliYWQtOGM5MjA0MmYxODZlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidGg2Q1czSTU4bDFcL3VVSkpwajd5Nm5kdTZYandFNlhCSVVkTDdVNUsybmV0T1JoMlBFS2trVzFpYVAwOVpCWWcifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.1.200.106] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Sai Chaganty Minor feedback - The comments surrounding the new APIs (Early PCH Init) is = not matching with the API function name (EarlySiliconInit). It's good to ke= ep them consistent. -----Original Message----- From: Desimone, Nathaniel L=20 Sent: Wednesday, November 13, 2019 10:07 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Kubacki, Michael A ; Chaganty, Rangasai V Subject: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add Silico= nInitLib SiliconInitLib contains Silicon Init APIs that can be reused by BoardInitLi= b. It is expected that several implementations of BoardInitLib exist for a = given SOC, these APIs allow the various BoardInitLib implementations to reu= se common silicon initialization code. This matches the implementation alre= ady found in KabylakeSiliconPkg. This change also adds halting the TCO watc= h dog timer to PEI, which was previously done in SEC. Cc: Chasel Chiu Cc: Michael Kubacki Cc: Sai Chaganty Signed-off-by: Nate DeSimone --- .../Include/Library/SiliconInitLib.h | 28 +++++ .../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++ .../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++ .../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++ 4 files changed, 202 insertions(+) create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/Sili= conInitLib.h create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/PeiSiliconInitLib.inf create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/SiliconInit.c create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/SiliconInitPreMem.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInit= Lib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h new file mode 100644 index 0000000000..a3411126a7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib. +++ h @@ -0,0 +1,28 @@ +/** @file++Copyright (c) 2019, Intel Corporation. All rights=20 +reserved.
+SPDX-License-Identifier:=20 +BSD-2-Clause-Patent++**/++#ifndef _SILICON_INIT_LIB_H_+#define=20 +_SILICON_INIT_LIB_H_++#include ++VOID+EarlySiliconInit (+ =20 +VOID+ );++VOID+SiliconInit (+ VOID+ );++VOID+LateSiliconInit (+ =20 +VOID+ );++#endif \ No newline at end of file diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/P= eiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSilico= nInitLib/PeiSiliconInitLib.inf new file mode 100644 index 0000000000..47da5f608b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi +++ liconInitLib.inf @@ -0,0 +1,46 @@ +### @file+#+# Copyright (c) 2019, Intel Corporation. All rights reserved.<= BR>+#+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+###++[Defines]+ INF= _VERSION =3D 0x00010017+ BASE_NAME = =3D SiliconInitLib+ FILE_GUID =3D 82F2ACF0-2EBE-48C8= -AC58-9D0F8BC1E16E+ VERSION_STRING =3D 1.0+ MODULE_TYPE = =3D PEIM+ LIBRARY_CLASS =3D SiliconInit= Lib+#+# The following information is for reference only and not required by= the build tools.+#+# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC+#++[LibraryC= lasses]+ BaseLib+ BaseMemoryLib+ DebugLib+ HobLib+ IoLib+ PcdLib+ Pe= iServicesLib+ PchCycleDecodingLib+ PmcLib++[Packages]+ MdePkg/MdePkg.dec= + CoffeelakeSiliconPkg/SiPkg.dec++[Sources]+ SiliconInit.c+ SiliconInitP= reMem.c++[Guids]+ gTcoWdtHobGuid ## CONSUMES+= +[Pcd]+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gSiPkgTo= kenSpaceGuid.PcdTcoBaseAddress ## CONSUMESdiff --git a/Silicon/Intel/C= offeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c b/Silicon/Intel= /CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c new file mode 100644 index 0000000000..122c02a3e5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic +++ onInit.c @@ -0,0 +1,19 @@ +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib=20 +implementations.++Copyright (c) 2019, Intel Corporation. All rights=20 +reserved.
+SPDX-License-Identifier:=20 +BSD-2-Clause-Patent++**/++#include ++/**+ Late PCH=20 +Init+**/+VOID+LateSiliconInit (+ VOID+ )+{+}diff --git=20 +a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI +nitPreMem.c=20 +b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI +nitPreMem.c new file mode 100644 index 0000000000..23e4a3d4a0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic +++ onInitPreMem.c @@ -0,0 +1,109 @@ +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib implementations= .++Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-Lic= ense-Identifier: BSD-2-Clause-Patent++**/++#include +#include +#include +#include +#in= clude +#include +#include +#include +#include +#include +#include ++= /**+ Early PCH initialization+**/+VOID+EarlySiliconInit (+ VOID+ )+{+ U= INT16 Data16;+ UINT8 Data8;+ UINT8 TcoRebootHappened;= + TCO_WDT_HOB *TcoWdtHobPtr;+ EFI_STATUS Status;++ ///+ /// LPC I/O = Configuration+ ///+ PchLpcIoDecodeRangesSet (+ (V_LPC_CFG_IOD_LPT_378 = << N_LPC_CFG_IOD_LPT) |+ (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COM= B) |+ (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)+ );++ PchLpcIo= EnableDecodingSet (+ B_LPC_CFG_IOE_ME2 |+ B_LPC_CFG_IOE_SE |+ B_L= PC_CFG_IOE_ME1 |+ B_LPC_CFG_IOE_KE |+ B_LPC_CFG_IOE_HGE |+ B_LPC_= CFG_IOE_LGE |+ B_LPC_CFG_IOE_FDE |+ B_LPC_CFG_IOE_PPE |+ B_LPC_CFG= _IOE_CBE |+ B_LPC_CFG_IOE_CAE+ );++ ///+ /// Halt the TCO timer+ /= //+ Data16 =3D IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT)= ;+ Data16 |=3D B_TCO_IO_TCO1_CNT_TMR_HLT;+ IoWrite16 (PcdGet16 (PcdTcoBas= eAddress) + R_TCO_IO_TCO1_CNT, Data16);++ ///+ /// Read the Second TO sta= tus bit+ ///+ Data8 =3D IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_= TCO2_STS);+ if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) =3D=3D B_TCO_IO_TCO2= _STS_SECOND_TO) {+ TcoRebootHappened =3D 1;+ DEBUG ((DEBUG_INFO, "Pla= tformInitPreMem - TCO Second TO status bit is set. This might be a TCO rebo= ot\n"));+ }+ else {+ TcoRebootHappened =3D 0;+ }++ ///+ /// Create = HOB+ ///+ Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, s= izeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);+ if (!EFI_ERROR (Status)) {+ = TcoWdtHobPtr->Header.Name =3D gTcoWdtHobGuid;+ TcoWdtHobPtr->TcoReboo= tHappened =3D TcoRebootHappened;+ }++ ///+ /// Clear the Second TO statu= s bit+ ///+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B= _TCO_IO_TCO2_STS_SECOND_TO);+}++/**+ Initialize the GPIO IO selection, GPI= O USE selection, and GPIO signal inversion registers++**/+VOID+SiliconInit = (+ VOID+ )+{+ UINT16 ABase;++ ABase =3D PmcGetAcpiBase ();++ ///= + /// Clear all pending SMI. On S3 clear power button enable so it will no= t generate an SMI.+ ///+ IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);+ IoWri= te32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);+}--=20 2.23.0.windows.1