From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web10.3312.1574405740567286152 for ; Thu, 21 Nov 2019 22:55:41 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: rangasai.v.chaganty@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2019 22:55:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,228,1571727600"; d="scan'208";a="381998687" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga005.jf.intel.com with ESMTP; 21 Nov 2019 22:55:39 -0800 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 21 Nov 2019 22:55:39 -0800 Received: from fmsmsx104.amr.corp.intel.com ([169.254.3.245]) by fmsmsx124.amr.corp.intel.com ([169.254.8.188]) with mapi id 14.03.0439.000; Thu, 21 Nov 2019 22:55:39 -0800 From: "Chaganty, Rangasai V" To: "Desimone, Nathaniel L" , "devel@edk2.groups.io" CC: "Chiu, Chasel" , "Kubacki, Michael A" Subject: Re: [edk2-platforms] [PATCH V2 06/14] CoffeelakeSiliconPkg: Add SiliconInitLib Thread-Topic: [edk2-platforms] [PATCH V2 06/14] CoffeelakeSiliconPkg: Add SiliconInitLib Thread-Index: AQHVoEn91L8A6KcCikqKZJeRIKaE56eWwu6g Date: Fri, 22 Nov 2019 06:55:38 +0000 Message-ID: References: <20191121085853.2626-1-nathaniel.l.desimone@intel.com> <20191121085853.2626-7-nathaniel.l.desimone@intel.com> In-Reply-To: <20191121085853.2626-7-nathaniel.l.desimone@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYmI4NDI4ZjgtMzE4YS00Yjc3LWFlYWEtMTIwYjI2OWVjMWY5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidloyS3VIcDg4UUJmWFRqek1PRjFVVDdCMUV0XC95T0hvNkwwaFZONTh3TGwyZ2huTHc5bUlYRE9iQjNaTE0yRzYifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.1.200.106] MIME-Version: 1.0 Return-Path: rangasai.v.chaganty@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Sai Chaganty -----Original Message----- From: Desimone, Nathaniel L=20 Sent: Thursday, November 21, 2019 12:59 AM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Kubacki, Michael A ; Chaganty, Rangasai V Subject: [edk2-platforms] [PATCH V2 06/14] CoffeelakeSiliconPkg: Add Silico= nInitLib SiliconInitLib contains Silicon Init APIs that can be reused by BoardInitLi= b. It is expected that several implementations of BoardInitLib exist for a = given SOC, these APIs allow the various BoardInitLib implementations to reu= se common silicon initialization code. This matches the implementation alre= ady found in KabylakeSiliconPkg. This change also adds halting the TCO watc= h dog timer to PEI, which was previously done in SEC. Cc: Chasel Chiu Cc: Michael Kubacki Cc: Sai Chaganty Signed-off-by: Nate DeSimone --- .../Include/Library/SiliconInitLib.h | 28 +++++ .../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++ .../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++ .../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++ 4 files changed, 202 insertions(+) create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/Sili= conInitLib.h create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/PeiSiliconInitLib.inf create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/SiliconInit.c create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/SiliconInitPreMem.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInit= Lib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h new file mode 100644 index 0000000000..a3411126a7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib. +++ h @@ -0,0 +1,28 @@ +/** @file++Copyright (c) 2019, Intel Corporation. All rights=20 +reserved.
+SPDX-License-Identifier:=20 +BSD-2-Clause-Patent++**/++#ifndef _SILICON_INIT_LIB_H_+#define=20 +_SILICON_INIT_LIB_H_++#include ++VOID+EarlySiliconInit (+ =20 +VOID+ );++VOID+SiliconInit (+ VOID+ );++VOID+LateSiliconInit (+ =20 +VOID+ );++#endif \ No newline at end of file diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/P= eiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSilico= nInitLib/PeiSiliconInitLib.inf new file mode 100644 index 0000000000..1534a24dd2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi +++ liconInitLib.inf @@ -0,0 +1,46 @@ +### @file+#+# Copyright (c) 2019, Intel Corporation. All rights reserved.<= BR>+#+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+###++[Defines]+ INF= _VERSION =3D 0x00010017+ BASE_NAME = =3D SiliconInitLib+ FILE_GUID =3D 82F2ACF0-2EBE-48C8= -AC58-9D0F8BC1E16E+ VERSION_STRING =3D 1.0+ MODULE_TYPE = =3D PEIM+ LIBRARY_CLASS =3D SiliconInit= Lib|SEC PEIM+#+# The following information is for reference only and not re= quired by the build tools.+#+# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC+#++= [LibraryClasses]+ BaseLib+ BaseMemoryLib+ DebugLib+ HobLib+ IoLib+ Pc= dLib+ PeiServicesLib+ PchCycleDecodingLib+ PmcLib++[Packages]+ MdePkg/M= dePkg.dec+ CoffeelakeSiliconPkg/SiPkg.dec++[Sources]+ SiliconInit.c+ Sil= iconInitPreMem.c++[Guids]+ gTcoWdtHobGuid ## = CONSUMES++[Pcd]+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ = gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMESdiff --git a/Silico= n/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c b/Sili= con/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c new file mode 100644 index 0000000000..1c15e0e54e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic +++ onInit.c @@ -0,0 +1,19 @@ +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib=20 +implementations.++Copyright (c) 2019, Intel Corporation. All rights=20 +reserved.
+SPDX-License-Identifier:=20 +BSD-2-Clause-Patent++**/++#include ++/**+ Late Silicon=20 +Initialization+**/+VOID+LateSiliconInit (+ VOID+ )+{+}diff --git=20 +a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI +nitPreMem.c=20 +b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI +nitPreMem.c new file mode 100644 index 0000000000..ab98b6ccc5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic +++ onInitPreMem.c @@ -0,0 +1,109 @@ +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib implementations= .++Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-Lic= ense-Identifier: BSD-2-Clause-Patent++**/++#include +#include +#include +#include +#in= clude +#include +#include +#include +#include +#include +#include ++= /**+ Early Silicon initialization+**/+VOID+EarlySiliconInit (+ VOID+ )+{= + UINT16 Data16;+ UINT8 Data8;+ UINT8 TcoRebootHappe= ned;+ TCO_WDT_HOB *TcoWdtHobPtr;+ EFI_STATUS Status;++ ///+ /// LPC = I/O Configuration+ ///+ PchLpcIoDecodeRangesSet (+ (V_LPC_CFG_IOD_LPT_= 378 << N_LPC_CFG_IOD_LPT) |+ (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD= _COMB) |+ (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)+ );++ PchL= pcIoEnableDecodingSet (+ B_LPC_CFG_IOE_ME2 |+ B_LPC_CFG_IOE_SE |+ = B_LPC_CFG_IOE_ME1 |+ B_LPC_CFG_IOE_KE |+ B_LPC_CFG_IOE_HGE |+ B_= LPC_CFG_IOE_LGE |+ B_LPC_CFG_IOE_FDE |+ B_LPC_CFG_IOE_PPE |+ B_LPC= _CFG_IOE_CBE |+ B_LPC_CFG_IOE_CAE+ );++ ///+ /// Halt the TCO timer= + ///+ Data16 =3D IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_= CNT);+ Data16 |=3D B_TCO_IO_TCO1_CNT_TMR_HLT;+ IoWrite16 (PcdGet16 (PcdTc= oBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);++ ///+ /// Read the Second TO= status bit+ ///+ Data8 =3D IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO= _IO_TCO2_STS);+ if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) =3D=3D B_TCO_IO_= TCO2_STS_SECOND_TO) {+ TcoRebootHappened =3D 1;+ DEBUG ((DEBUG_INFO, = "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO = reboot\n"));+ }+ else {+ TcoRebootHappened =3D 0;+ }++ ///+ /// Cre= ate HOB+ ///+ Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSIO= N, sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);+ if (!EFI_ERROR (Status))= {+ TcoWdtHobPtr->Header.Name =3D gTcoWdtHobGuid;+ TcoWdtHobPtr->TcoR= ebootHappened =3D TcoRebootHappened;+ }++ ///+ /// Clear the Second TO s= tatus bit+ ///+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_ST= S, B_TCO_IO_TCO2_STS_SECOND_TO);+}++/**+ Initialize the GPIO IO selection,= GPIO USE selection, and GPIO signal inversion registers++**/+VOID+SiliconI= nit (+ VOID+ )+{+ UINT16 ABase;++ ABase =3D PmcGetAcpiBase ();++ = ///+ /// Clear all pending SMI. On S3 clear power button enable so it wil= l not generate an SMI.+ ///+ IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);+ I= oWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);+}--=20 2.24.0.windows.2