From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Permerror (SPF Permanent Error: More than 10 MX records returned) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=qin.long@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AE352221EA0A5 for ; Thu, 7 Dec 2017 18:15:51 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Dec 2017 18:20:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,375,1508828400"; d="scan'208";a="16447232" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 07 Dec 2017 18:20:24 -0800 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 7 Dec 2017 18:20:24 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 7 Dec 2017 18:20:23 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.152]) with mapi id 14.03.0319.002; Fri, 8 Dec 2017 10:20:22 +0800 From: "Long, Qin" To: "Zhang, Chao B" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" , "Zhang, Chao B" Thread-Topic: [edk2] [PATCH] SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt support Thread-Index: AQHTb73AlhpkoKykWE65mNFJ0EvBPKM4tqFg Date: Fri, 8 Dec 2017 02:20:21 +0000 Message-ID: References: <20171208004434.50468-1-chao.b.zhang@intel.com> In-Reply-To: <20171208004434.50468-1-chao.b.zhang@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Dec 2017 02:15:52 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Long Qin Best Regards & Thanks, LONG, Qin -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Zhan= g, Chao B Sent: Friday, December 8, 2017 8:45 AM To: edk2-devel@lists.01.org Cc: Yao, Jiewen ; Zhang, Chao B ; Long, Qin Subject: [edk2] [PATCH] SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt sup= port 1. Report TPM SIRQ interrupt resource through _CRS 2. Expose _SRS to update= interrupt resource & FIFO/TIS interrupt related registers defined in TCG PC Client Platform TPM Profile (PTP) Specification spec h= ttps://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Plat= form-TPM-Profile-for-TPM-2-0-v43-150126.pdf Note: IHV/OEM need to carefully verify this feature with OS TPM driver to m= ake sure there is no impact to system/HW Cc: Long Qin Cc: Jiewen Yao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang --- SecurityPkg/Tcg/Tcg2Smm/Tpm.asl | 112 ++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 104 insertions(+), 8 deletions(-) diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl b/SecurityPkg/Tcg/Tcg2Smm/Tpm.= asl index cf0642e..68b5073 100644 --- a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl +++ b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl @@ -44,13 +44,6 @@ DefinitionBlock ( Name (_STR, Unicode ("TPM 2.0 Device")) =20 // - // Return the resource consumed by TPM device - // - Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - - // // Operational region for Smi port access // OperationRegion (SMIP, SystemIO, 0xB2, 1) @@ -65,7 +58,19 @@ Definit= ionBlock ( OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000) Field (TPMR, AnyAcc, NoLock, Preserve) { - ACC0, 8, + ACC0, 8, // TPM_ACCESS_0 + Offset(0x8), + INTE, 32, // TPM_INT_ENABLE_0 + INTV, 8, // TPM_INT_VECTOR_0 + Offset(0x10), + INTS, 32, // TPM_INT_STATUS_0 + INTF, 32, // TPM_INTF_CAPABILITY_0 + STS0, 32, // TPM_STS_0 + Offset(0x24), + FIFO, 32, // TPM_DATA_FIFO_0 + Offset(0x30), + TID0, 32, // TPM_INTERFACE_ID_0 + // ignore the rest } =20 // @@ -89,6 +94,97 @@ DefinitionBlock ( UCRQ, 32 // Phyical Presence request operation to Get User Co= nfirmation Status=20 } =20 + Name(RESO, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {12= } + }) + + // + // Return the resource consumed by TPM device. + // + Method(_CRS,0,Serialized) + { + Return(RESO) + } + + // + // Set resources consumed by the TPM device. This is used to + // assign an interrupt number to the device. The input byte stream + // has to be the same as returned by _CRS (according to ACPI spec). + // + Method(_SRS,1,Serialized) + { + // + // Update resource descriptor + // Use the field name to identify the offsets in the argument + // buffer and RESO buffer. + // + CreateDWordField(Arg0, ^IRQ._INT, IRQ0) + CreateDWordField(RESO, ^IRQ._INT, LIRQ) + Store(IRQ0, LIRQ) + + CreateBitField(Arg0, ^IRQ._HE, ITRG) + CreateBitField(RESO, ^IRQ._HE, LTRG) + Store(ITRG, LTRG) + + CreateBitField(Arg0, ^IRQ._LL, ILVL) + CreateBitField(RESO, ^IRQ._LL, LLVL) + Store(ILVL, LLVL) + + // + // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTER= FACE_ID_x lowest + // nibble. + // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active + // 1111 - FIFO interface as defined in TIS1.3 is active + // + If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F),= 0x0F))) { + // + // If FIFO interface, interrupt vector register is + // available. TCG PTP specification allows only + // values 1..15 in this field. For other interrupts + // the field should stay 0. + // + If (LLess (IRQ0, 16)) { + Store (And(IRQ0, 0xF), INTV) + } + // + // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4 + // contains settings for interrupt polarity. + // The other bits of the byte enable individual interrupts. + // They should be all be zero, but to avoid changing the + // configuration, the other bits are be preserved. + // 00 - high level + // 01 - low level + // 10 - rising edge + // 11 - falling edge + // + // ACPI spec definitions: + // _HE: '1' is Edge, '0' is Level + // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG s= pec) + // + If (LEqual (ITRG, 1)) { + Or(INTE, 0x00000010, INTE) + } Else { + And(INTE, 0xFFFFFFEF, INTE) + } + if (LEqual (ILVL, 0)) { + Or(INTE, 0x00000008, INTE) + } Else { + And(INTE, 0xFFFFFFF7, INTE) + } + } + } + + // + // Possible resource settings. + // The format of the data has to follow the same format as + // _CRS (according to ACPI spec). + // + Name (_PRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , SIRQ) {1= ,2,3,4,5,6,7,8,9,10,11,12,13,14,15} + }) + Method (PTS, 1, Serialized) { =20 // -- 1.9.5.msysgit.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel