From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.6854.1589432793136902311 for ; Wed, 13 May 2020 22:06:33 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=Dpb9gKAr; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: nathaniel.l.desimone@intel.com) IronPort-SDR: wb6kTeMgYXaa5+3aubk/uV/+e3gJsgXL8lTGE2grROr8QNp8EXoAdXp3soE6JSlgvG6/CBCW0o uD3ap3xpnaNw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2020 22:06:30 -0700 IronPort-SDR: b5oEhq7jhUJQE/Y/YaveYm1hDcRRSBKNHte+LXu8+vZ3kD9c42JqGgXaG0W38UULRYUQPSMRed bI7BIt4eYIqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,390,1583222400"; d="scan'208";a="280736160" Received: from orsmsx106.amr.corp.intel.com ([10.22.225.133]) by orsmga002.jf.intel.com with ESMTP; 13 May 2020 22:06:29 -0700 Received: from orsmsx163.amr.corp.intel.com (10.22.240.88) by ORSMSX106.amr.corp.intel.com (10.22.225.133) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 13 May 2020 22:06:29 -0700 Received: from ORSEDG002.ED.cps.intel.com (10.7.248.5) by ORSMSX163.amr.corp.intel.com (10.22.240.88) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 13 May 2020 22:06:29 -0700 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.169) by edgegateway.intel.com (134.134.137.101) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 13 May 2020 22:06:29 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HHGlzglcNCUEx9EHkcyRq+e77XHwTdYEz0XRz7x1O14N6vQh7+bEAVNFB6wzIqCs4lzBDClkannC+WrSrVlLQFD7n6OUe2GvxNt81JpX9CwpQ7ItTlywpWAA3IHtExL1o4UuQPB8Jm9hD9vZtQAsuaa0PoFx9Fet96WSP4EbMBAIlarsXfwQ2UE86ybaXk8ZQIuEYnCSaRkFOzs6gxZwxk6LYolAuLMwI66kcxO2eov0fkaUevTjp6xDharpwt57xmz09mU9FX2kORd2tR1+k0GKq3R6W4wha935qlvhfvUkyv310hDSRJUZThbdbF3ksS5I+iO+ISJD0KYeqctDFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6NXN+ETQCS9yYswKIOGqzIHSmhb2+bo6k0pxcypn0x0=; b=KoJfmY8HdgZq5SCEVoLQKxyqyjEKPKJ4FtJ/vGXjAT2TUqAf0mq4j0T9dco0+MrU7/dBrHzfTbnPIs7JtGFWb4ylLQLQUod84DfxfeSatGpyNxV0vIR/Cg5ci/FM8UzvEkagSNwKCT1d5EbBidMlqj26irkvSpJmxxcLRly6Ur2FGXdkRVj4Wf+F0S5DIltr+ab77h/zDq209cCGf6lnSjq5pCmyF/h8sT2PJWhvMu2r7YizbVYpIuWJaTFp6Pg9g2R49p2+FSUFWWZMTB7hbhGYD2mljMZV82x3jyjpfyY49x5b2zZla/qQPwVjK98caHq0EA2o4/MXEgvsKv3rkA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6NXN+ETQCS9yYswKIOGqzIHSmhb2+bo6k0pxcypn0x0=; b=Dpb9gKArIptVKlcO3fx3C0jlP+MTww3xr4KXsbTNgn6dYGeltyGCVyeNPx97ofzGoRwlWZdkoBGXonRB66n2X1x0QjsRl4W8i5fVG1fugF0FWO06rA+aKxIiKcWmYgh0T4Yjv6U9GWNOfnSZXEEyWHOxftusWoII2E1Wh7TUBuQ= Received: from BL0PR11MB3489.namprd11.prod.outlook.com (2603:10b6:208:75::29) by BL0PR11MB3348.namprd11.prod.outlook.com (2603:10b6:208:6a::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.24; Thu, 14 May 2020 05:06:27 +0000 Received: from BL0PR11MB3489.namprd11.prod.outlook.com ([fe80::d0f8:bfd7:bae2:3e42]) by BL0PR11MB3489.namprd11.prod.outlook.com ([fe80::d0f8:bfd7:bae2:3e42%7]) with mapi id 15.20.2979.033; Thu, 14 May 2020 05:06:27 +0000 From: "Nate DeSimone" To: "devel@edk2.groups.io" , "Chiu, Chasel" CC: "Ma, Maurice" , "Zeng, Star" Subject: Re: [edk2-devel] [PATCH v8] IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers. Thread-Topic: [edk2-devel] [PATCH v8] IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers. Thread-Index: AQHWKTXwsxSVZIg3SEO3bbHPIVXSZ6inB25A Date: Thu, 14 May 2020 05:06:26 +0000 Message-ID: References: <20200513145019.13504-1-chasel.chiu@intel.com> In-Reply-To: <20200513145019.13504-1-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWQ4OGIyODMtZThkMS00ZGMzLWI5ODMtMTI3ZTQzN2VlOGQwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidGMrYmxKTUh3bHdQaTZpa01qWG5ybmdqRnlDRkpxcGI4b2d5MWJ2djNXd1VPQVgxVUFkV0xlOTFneENnVFwvVlwvIn0= dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows x-ctpclassification: CTP_NT authentication-results: edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=intel.com; x-originating-ip: [50.53.190.176] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bd43b856-a4dc-4c17-e65b-08d7f7c48ea6 x-ms-traffictypediagnostic: BL0PR11MB3348: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 040359335D x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: eKUwwuMVQtlwSGK6icG5Au0Oe3/6EcimIbah9o8xQ73Xsu5f2M9K8J38MreJEuLn+cmUWNqJFdrcXE985gZYI68KjEYawS/eoDYjM/vxCVptYSogahplrI6kZj/14ytigjy/skLShD1ze4YRYaMU9r5tl0dX4n2lI880oVpw7wRAlBvRgAfKSj5vLd0f/u1YPGNOG5lSMh7sVYnjSXYX/1r/utSBkKYHzCEBXW2mhtPooP4+bw0liWJM171WvC1Bgudl2saFbFkjZ5+zSQTYiRqZmfOftcigxX/ewWyTWtqyVHdduU5bYRlE9I27tl8Pe773xPoogfBPgHQldnEZ1L6FCiqKCgT9HaqThTg4AoTi3q2QdwFfKaOwpz3BztwvVb7xlM6zEV2HDzDTpV90HVDnS+LU3ZLZz3gbhStvymhLmyspc/MaY3yniKXKxzcQcFQ+DNGu5X1TxJn4XA4vM2OE46rrvkYwWy5Adb0yNdJt8nV38Zlz2DPzhl7NSweGkc0gw6z6uI+uqaFqzIh/6Q== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BL0PR11MB3489.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(6029001)(136003)(346002)(366004)(376002)(39860400002)(396003)(4326008)(110136005)(52536014)(6636002)(8676002)(30864003)(76116006)(316002)(9686003)(107886003)(71200400001)(54906003)(7696005)(53546011)(6506007)(33656002)(26005)(55016002)(8936002)(66476007)(66556008)(186003)(64756008)(19627235002)(5660300002)(66446008)(478600001)(86362001)(966005)(2906002)(66946007)(559001)(579004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: ymj0hLjE8iou6goWC+fNeKmhnGaJ9LObaYPWDbM17wjtuS7TO2a13y9GCFDEtzF7jKR2zJe92b8UNSu9CIZ182G5Lr75GIk3ys3vFnY0ZW0epGTc21j/nTIadVV4tC/HFtzAmwiw7IDi6td7I0JDclYHTOf3tNCizjlGzrNW5cT43L5sS8JQ6dJo7cMboi1Wi/99VoaSO+ERgqN128Grsz3pIPyg+TCGGZbhHCbhC4ilnhUKZaTTHqZiY2KYI9+kNJreZvOzKOkoBIrZ8XL3E0hJcQpYaOeCB7xxy2rMLvwdO9yqSk2TcUFVXl0r8bR6cbVd5vLK34WnptujkLRJpe+Fh0DqMuZ1iLxWjqBMweF94VmkI41Oi7NeYgE5fOjLMq8T9C5b+cIbxDzYYyxZjg7sIDSHWtA35LpYltp/MMRnp1JEfvLdvRABCaGU4YtCQ8Bq1ywb675j1/Nq7HywXPzQjQ1nHzO6HpwS1o5HGJsz5R0FGQAbxNyTM1fZsUOi MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: bd43b856-a4dc-4c17-e65b-08d7f7c48ea6 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 May 2020 05:06:26.9620 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: DjYm5mgUeby4/hKKUW6YTtU4CrHx1ExpBIHtO6CXjIVOjutRAkxv6dxiUuGiABsBaUuRLAoihN+COCk7qzsWFhdKkFywMlf+zHJ1387xFM0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR11MB3348 Return-Path: nathaniel.l.desimone@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Chasel, Two minor comments. #1) The following comment: // Usually OnSeparateStack can be reset when FSP-M returning control bac= k to bootloader and after // that FSP again has a chance to run on the same bootloader stack. This is not quite accurate. Once we switch to the separate stack, we can n= ever come back to bootloader stack. The reason why is because all the PEI c= ore global data (List of PEIMs, PPI list, etc.) is stored in the stack. Bec= ause those data structure use several pointers, all the PEI core state need= s to be relocated/fixed up if the stack base changes. The only reason this works OK is because the PeiCore() function never retu= rns. #2) I think Reserved4[26] should be Reserved4[20]. Please see inline. With those changes... Reviewed-by: Nate DeSimone The only opportunity we have to fixup the PEI global state is during the f= low that shadows PEI to DRAM, since that requires us to relocate PEI core a= nyway. So once OneSeperateStack becomes 1... it can never go back to 0 with= out a platform reset. > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Chiu, > Chasel > Sent: Wednesday, May 13, 2020 7:50 AM > To: devel@edk2.groups.io > Cc: Ma, Maurice ; Desimone, Nathaniel L > ; Zeng, Star > Subject: [edk2-devel] [PATCH v8] IntelFsp2Pkg: Support Multi-Phase SiIni= t > and debug handlers. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2698 >=20 > To enhance FSP silicon initialization flexibility an optional Multi-Phas= e API is > introduced and FSP header needs update for new API offset. Also new > SecCore module created for FspMultiPhaseSiInit API >=20 > New ARCH_UPD introduced for enhancing FSP debug message flexibility now > bootloader can pass its own debug handler function pointer and FSP will = call > the function to handle debug message. > To support calling bootloader functions, a FspGlobalData field added to > indicate if FSP needs to switch stack when FSP running on separate stack > from bootloader. >=20 > Cc: Maurice Ma > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Chasel Chiu > --- >=20 > V8: > Add OnSeparateStack FspGlobalData field to indicate if FSP running on > bootloader stack or not. When FSP calling bootloader functions switching > stack is necessary when FSP running on separate stack. >=20 > IntelFsp2Pkg/FspSecCore/SecFsp.c | 1= 2 +++++++++++- > IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | = 6 +++--- > IntelFsp2Pkg/FspSecCore/SecMain.c | 1= 0 +++++++++- > IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c | 1= 9 > ++++++++++++++++++- > IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 5= 2 > ++++++++++++++++++++++++++++++++++++++++++++++++++++ > IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm | 9= 9 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++ > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | = 5 > ++++- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 13= 0 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++--- > IntelFsp2Pkg/Include/FspGlobalData.h | 1= 1 ++++++++--- > IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 1= 0 ++++++++-- > IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h | 1= 6 > +++++++++++++++- > 11 files changed, 354 insertions(+), 16 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c > b/IntelFsp2Pkg/FspSecCore/SecFsp.c > index 446d1730e9..216f7bb6c5 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved. > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -161,6 +161,16 @@ FspGlobalDataInit ( > SetFspSiliconInitUpdDataPointer (NULL); >=20 > // > + // Initialize OnSeparateStack value. > + // > + if (PcdGet8 (PcdFspHeapSizePercentage) !=3D 0) { > + // > + // FSP is running on its own stack and may need switching stack whe= n > calling bootloader functions. > + // > + GetFspGlobalDataPointer ()->OnSeparateStack =3D 1; } > + > + // > // Initialize serial port > // It might have been done in ProcessLibraryConstructorList(), howeve= r, > // the FSP global data is not initialized at that time. So do it agai= n diff --git > a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > index 8e0595fe9a..1334959005 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved. > + Copyright (c) 2016 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -59,7 +59,7 @@ FspApiCallingCheck ( > Status =3D EFI_UNSUPPORTED; > } > } > - } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) { > + } else if ((ApiIdx =3D=3D FspSiliconInitApiIndex) || (ApiIdx =3D=3D > + FspMultiPhaseSiInitApiIndex)) { > // > // FspSiliconInit check > // > @@ -68,7 +68,7 @@ FspApiCallingCheck ( > } else { > if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) { > Status =3D EFI_UNSUPPORTED; > - } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) { > + } else if (EFI_ERROR (FspUpdSignatureCheck > + (FspSiliconInitApiIndex, ApiParam))) { > Status =3D EFI_INVALID_PARAMETER; > } > } > diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c > b/IntelFsp2Pkg/FspSecCore/SecMain.c > index 7169afc6c7..300f93ebab 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.c > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved. > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -221,6 +221,14 @@ SecTemporaryRamSupport ( > UINTN CurrentStack; > UINTN FspStackBase; >=20 > + // > + // Override OnSeparateStack to 1 because this function will switch > + stack to permanent memory which // makes FSP running on different > stack from bootloader temp ram stack. > + // Usually OnSeparateStack can be reset when FSP-M returning control > + back to bootloader and after // that FSP again has a chance to run on= the > same bootloader stack. > + // > + GetFspGlobalDataPointer ()->OnSeparateStack =3D 1; > + > if (PcdGet8 (PcdFspHeapSizePercentage) =3D=3D 0) { >=20 > CurrentStack =3D AsmReadEsp(); > diff --git > a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > index f7945b5240..df8c5d121f 100644 > --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > @@ -1,7 +1,7 @@ > /** @file > Null instance of Platform Sec Lib. >=20 > - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved. > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -25,3 +25,20 @@ FspUpdSignatureCheck ( { > return EFI_SUCCESS; > } > + > +/** > + This function handles FspMultiPhaseSiInitApi. > + > + @param[in] ApiIdx Internal index of the FSP API. > + @param[in] ApiParam Parameter of the FSP API. > + > +**/ > +EFI_STATUS > +EFIAPI > +FspMultiPhaseSiInitApiHandler ( > + IN UINT32 ApiIdx, > + IN VOID *ApiParam > + ) > +{ > + return EFI_SUCCESS; > +} > diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf > b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf > new file mode 100644 > index 0000000000..0a24eb2a8b > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf > @@ -0,0 +1,52 @@ > +## @file > +# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitializat= ion. > +# > +# Copyright (c) 2020, Intel Corporation. All rights reserved.
# # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D Fsp22SecCoreS > + FILE_GUID =3D DF0FCD70-264A-40BF-BBD4-06C76DB19C= B1 > + MODULE_TYPE =3D SEC > + VERSION_STRING =3D 1.0 > + > +# > +# The following information is for reference only and not required by t= he > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 > +# > + > +[Sources] > + SecFspApiChk.c > + SecFsp.h > + > +[Sources.IA32] > + Ia32/Stack.nasm > + Ia32/Fsp22ApiEntryS.nasm > + Ia32/FspApiEntryCommon.nasm > + Ia32/FspHelper.nasm > + > +[Binaries.Ia32] > + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC > + > +[Packages] > + MdePkg/MdePkg.dec > + IntelFsp2Pkg/IntelFsp2Pkg.dec > + > +[LibraryClasses] > + BaseMemoryLib > + DebugLib > + BaseLib > + PciCf8Lib > + SerialPortLib > + FspSwitchStackLib > + FspCommonLib > + FspSecPlatformLib > + > +[Ppis] > + gEfiTemporaryRamSupportPpiGuid ## PRODUC= ES > + > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm > new file mode 100644 > index 0000000000..c5e73a635b > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm > @@ -0,0 +1,99 @@ > +;; @file > +; Provide FSP API entry points. > +; > +; Copyright (c) 2020, Intel Corporation. All rights reserved.
; > +SPDX-License-Identifier: BSD-2-Clause-Patent ;; > + > + SECTION .text > + > +; > +; Following functions will be provided in C ; extern > +ASM_PFX(FspApiCommon) extern > ASM_PFX(FspMultiPhaseSiInitApiHandler) > + > +;---------------------------------------------------------------------- > +------ > +; NotifyPhase API > +; > +; This FSP API will notify the FSP about the different phases in the > +boot ; process ; > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(NotifyPhaseApi) > +ASM_PFX(NotifyPhaseApi): > + mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex > + jmp ASM_PFX(FspApiCommon) > + > +;---------------------------------------------------------------------- > +------ > +; FspSiliconInit API > +; > +; This FSP API initializes the CPU and the chipset including the IO ; > +controllers in the chipset to enable normal operation of these devices. > +; > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(FspSiliconInitApi) > +ASM_PFX(FspSiliconInitApi): > + mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex > + jmp ASM_PFX(FspApiCommon) > + > +;---------------------------------------------------------------------- > +------ > +; FspMultiPhaseSiInitApi API > +; > +; This FSP API provides multi-phase silicon initialization, which > +brings greater ; modularity beyond the existing FspSiliconInit() API. > +; Increased modularity is achieved by adding an extra API to FSP-S. > +; This allows the bootloader to add board specific initialization steps > +throughout ; the SiliconInit flow as needed. > +; > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(FspMultiPhaseSiInitApi) > +ASM_PFX(FspMultiPhaseSiInitApi): > + mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex > + jmp ASM_PFX(FspApiCommon) > + > +;---------------------------------------------------------------------- > +------ > +; FspApiCommonContinue API > +; > +; This is the FSP API common entry point to resume the FSP execution ; > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(FspApiCommonContinue) > +ASM_PFX(FspApiCommonContinue): > + ; > + ; Handle FspMultiPhaseSiInitApiIndex API > + ; > + cmp eax, 6 > + jnz NotMultiPhaseSiInitApi > + > + pushad > + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam > + push eax ; push ApiIdx > + call ASM_PFX(FspMultiPhaseSiInitApiHandler) > + add esp, 8 > + mov dword [esp + (4 * 7)], eax > + popad > + ret > + > +NotMultiPhaseSiInitApi: > + jmp $ > + ret > + > +;---------------------------------------------------------------------- > +------ > +; TempRamInit API > +; > +; Empty function for WHOLEARCHIVE build option ; > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(TempRamInitApi) > +ASM_PFX(TempRamInitApi): > + jmp $ > + ret > + > +;---------------------------------------------------------------------- > +------ > +; Module Entrypoint API > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(_ModuleEntryPoint) > +ASM_PFX(_ModuleEntryPoint): > + jmp $ > + > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > index bb4451b145..26ae7d9fd3 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > @@ -1,7 +1,7 @@ > ;; @file > ; Provide FSP API entry points. > ; > -; Copyright (c) 2016, Intel Corporation. All rights reserved.
> +; Copyright (c) 2016 - 2020, Intel Corporation. All rights > +reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ;; >=20 > @@ -62,6 +62,9 @@ FspApiCommon2: > cmp eax, 3 ; FspMemoryInit API > jz FspApiCommon3 >=20 > + cmp eax, 6 ; FspMultiPhaseSiInitApiIndex API > + jz FspApiCommon3 > + > call ASM_PFX(AsmGetFspInfoHeader) > jmp ASM_PFX(Loader2PeiSwitchStack) >=20 > diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h > b/IntelFsp2Pkg/Include/FspEas/FspApi.h > index dcf489dbe6..ed40f9538c 100644 > --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h > +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h > @@ -1,8 +1,8 @@ > /** @file > Intel FSP API definition from Intel Firmware Support Package External > - Architecture Specification v2.0. > + Architecture Specification v2.0 - v2.2 >=20 > - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved. > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -10,6 +10,8 @@ > #ifndef _FSP_API_H_ > #define _FSP_API_H_ >=20 > +#include > + > /// > /// FSP Reset Status code > /// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code = @@ - > 24,6 +26,65 @@ > #define FSP_STATUS_RESET_REQUIRED_8 0x40000008 > /// @} >=20 > +/// > +/// FSP Event related definition. > +/// > +#define FSP_EVENT_CODE 0xF5000000 > +#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000) > + > +/* > + FSP may optionally include the capability of generating events messag= es to > aid in the debugging of firmware issues. > + These events fall under three catagories: Error, Progress, and Debug. > +The event reporting mechanism follows the > + status code services described in section 6 and 7 of the PI Specifica= tion v1.7 > Volume 3. > + > + @param[in] Type Indicates the type of event being r= eported. > + See MdePkg/Include/Pi/PiStatusCode.= h for the definition > of EFI_STATUS_CODE_TYPE. > + @param[in] Value Describes the current status of a h= ardware or > software entity. > + This includes information about the= class and subclass that > is used to classify the entity as well as an operation. > + For progress events, the operation = is the current activity. > For error events, it is the exception. > + For debug events, it is not defined= at this time. > + See MdePkg/Include/Pi/PiStatusCode.= h for the definition > of EFI_STATUS_CODE_VALUE. > + @param[in] Instance The enumeration of a hardware or so= ftware > entity within the system. > + A system may contain multiple entit= ies that match a > class/subclass pairing. The instance differentiates between them. > + An instance of 0 indicates that ins= tance information is > unavailable, not meaningful, or not relevant. > + Valid instance numbers start with 1= . > + @param[in] *CallerId This parameter can be used to ident= ify the > sub-module within the FSP generating the event. > + This parameter may be NULL. > + @param[in] *Data This optional parameter may be used= to pass > additional data. The contents can have event-specific data. > + For example, the FSP provides a > EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending > debug messages. > + This parameter is NULL when no addi= tional data is > provided. > + > + @retval EFI_SUCCESS The event was handled successfully. > + @retval EFI_INVALID_PARAMETER Input parameters are invalid. > + @retval EFI_DEVICE_ERROR The event handler failed. > +*/ > +typedef > +EFI_STATUS > +(EFIAPI *FSP_EVENT_HANDLER) ( > + IN EFI_STATUS_CODE_TYPE Type, > + IN EFI_STATUS_CODE_VALUE Value, > + IN UINT32 Instance, > + IN OPTIONAL EFI_GUID *CallerId, > + IN OPTIONAL EFI_STATUS_CODE_DATA *Data > + ); > + > +/* > + Handler for FSP-T debug log messages, provided by the bootloader. > + > + @param[in] DebugMessage A pointer to the debug message to b= e > written to the log. > + @param[in] MessageLength Number of bytes to written to the d= ebug > log. > + > + @retval UINT32 The return value indicates the numb= er of bytes > actually written to > + the debug log. If the return value = is less than > MessageLength, > + an error occurred. > +*/ > +typedef > +UINT32 > +(EFIAPI *FSP_DEBUG_HANDLER) ( > + IN CHAR8* DebugMessage, > + IN UINT32 MessageLength > + ); > + > #pragma pack(1) > /// > /// FSP_UPD_HEADER Configuration. > @@ -77,7 +138,12 @@ typedef struct { > /// Current boot mode. > /// > UINT32 BootMode; > - UINT8 Reserved1[8]; > + /// > + /// Optional event handler for the bootloader to be informed of event= s > occurring during FSP execution. > + /// This value is only valid if Revision is >=3D 2. > + /// > + FSP_EVENT_HANDLER *FspEventHandler; > + UINT8 Reserved1[4]; > } FSPM_ARCH_UPD; >=20 > /// > @@ -147,6 +213,40 @@ typedef struct { > FSP_INIT_PHASE Phase; > } NOTIFY_PHASE_PARAMS; >=20 > +/// > +/// Action definition for FspMultiPhaseSiInit API /// typedef enum { > + EnumMultiPhaseGetNumberOfPhases =3D 0x0, > + EnumMultiPhaseExecutePhase =3D 0x1 > +} FSP_MULTI_PHASE_ACTION; > + > +/// > +/// Data structure returned by FSP when bootloader calling /// > +FspMultiPhaseSiInit API with action 0 > (EnumMultiPhaseGetNumberOfPhases) > +/// typedef struct { > + UINT32 NumberOfPhases; > + UINT32 PhasesExecuted; > +} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS; > + > +/// > +/// FspMultiPhaseSiInit function parameter. > +/// > +/// For action 0 (EnumMultiPhaseGetNumberOfPhases): > +/// - PhaseIndex must be 0. > +/// - MultiPhaseParamPtr should point to an instance of > FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS. > +/// > +/// For action 1 (EnumMultiPhaseExecutePhase): > +/// - PhaseIndex will be the phase that will be executed by FSP. > +/// - MultiPhaseParamPtr shall be NULL. > +/// > +typedef struct { > + IN FSP_MULTI_PHASE_ACTION MultiPhaseAction; > + IN UINT32 PhaseIndex; > + IN OUT VOID *MultiPhaseParamPtr; > +} FSP_MULTI_PHASE_PARAMS; > + > #pragma pack() >=20 > /** > @@ -279,4 +379,28 @@ EFI_STATUS > IN VOID *FspsUpdDataPtr > ); >=20 > +/** > + This FSP API is expected to be called after FspSiliconInit but before > FspNotifyPhase. > + This FSP API provides multi-phase silicon initialization; which > +brings greater modularity > + beyond the existing FspSiliconInit() API. Increased modularity is > +achieved by adding an > + extra API to FSP-S. This allows the bootloader to add board specific > +initialization steps > + throughout the SiliconInit flow as needed. > + > + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - > EnumMultiPhaseGetNumberOfPhases: > + FSP_MULTI_PHASE_PARAMS->Mul= tiPhaseParamPtr > will contain > + how many phases supported b= y FSP. > + For action - EnumMultiPhaseEx= ecutePhase: > + FSP_MULTI_PHASE_PARAMS->Mul= tiPhaseParamPtr > shall be NULL. > + @retval EFI_SUCCESS FSP execution environment was= initialized > successfully. > + @retval EFI_INVALID_PARAMETER Input parameters are invalid. > + @retval EFI_UNSUPPORTED The FSP calling conditions we= re not > met. > + @retval EFI_DEVICE_ERROR FSP initialization failed. > + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These > status codes will not be returned during S3. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *FSP_MULTI_PHASE_SI_INIT) ( > + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr > +); > + > #endif > diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h > b/IntelFsp2Pkg/Include/FspGlobalData.h > index 1896b0240a..34a3793ace 100644 > --- a/IntelFsp2Pkg/Include/FspGlobalData.h > +++ b/IntelFsp2Pkg/Include/FspGlobalData.h > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -22,6 +22,7 @@ typedef enum { > FspMemoryInitApiIndex, > TempRamExitApiIndex, > FspSiliconInitApiIndex, > + FspMultiPhaseSiInitApiIndex, > FspApiIndexMax > } FSP_API_INDEX; >=20 > @@ -52,10 +53,14 @@ typedef struct { > VOID *SiliconInitUpdPtr; > UINT8 ApiIdx; > UINT8 FspMode; // 0: FSP in API mode; 1: FSP in DISPATC= H mode > - UINT8 Reserved3[30]; > + UINT8 OnSeparateStack; > + UINT8 Reserved3; > + UINT32 NumberOfPhases; > + UINT32 PhasesExecuted; > + UINT8 Reserved4[26]; I think this should be Reserved4[20]; > UINT32 PerfSig; > UINT16 PerfLen; > - UINT16 Reserved4; > + UINT16 Reserved5; > UINT32 PerfIdx; > UINT64 PerfData[32]; > } FSP_GLOBAL_DATA; > diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > index 16f43a1273..3474bac1de 100644 > --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > @@ -1,8 +1,8 @@ > /** @file > Intel FSP Header File definition from Intel Firmware Support Package > External > - Architecture Specification v2.0. > + Architecture Specification v2.0 and above. >=20 > - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -110,6 +110,12 @@ typedef struct { > /// Byte 0x44: The offset for the API to initialize the CPU and chips= et. > /// > UINT32 FspSiliconInitEntryOffset; > + /// > + /// Byte 0x48: Offset for the API for the optional Multi-Phase proces= sor > and chipset initialization. > + /// This value is only valid if FSP HeaderRevision is >=3D= 5. > + /// If the value is set to 0x00000000, then this API is no= t available in > this component. > + /// > + UINT32 FspMultiPhaseSiInitEntryOffset; > } FSP_INFO_HEADER; >=20 > /// > diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > index 4d01b5f6d9..51a0309aed 100644 > --- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. > + Copyright (c) 2015 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -79,4 +79,18 @@ FspUpdSignatureCheck ( > IN VOID *ApiParam > ); >=20 > +/** > + This function handles FspMultiPhaseSiInitApi. > + > + @param[in] ApiIdx Internal index of the FSP API. > + @param[in] ApiParam Parameter of the FSP API. > + > +**/ > +EFI_STATUS > +EFIAPI > +FspMultiPhaseSiInitApiHandler ( > + IN UINT32 ApiIdx, > + IN VOID *ApiParam > + ); > + > #endif > -- > 2.13.3.windows.1 >=20 >=20 >=20