From: Haojian Zhuang <haojian.zhuang@linaro.org>
To: "Tian, Feng" <feng.tian@intel.com>,
"leif.lindholm@linaro.org" <leif.lindholm@linaro.org>,
"ard.biesheuvel@linaro.org" <ard.biesheuvel@linaro.org>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "Tian, Feng" <feng.tian@intel.com>
Subject: Re: [PATCH 4/9] Ufs: fix to set UTRLBA and UTRLBAU register
Date: Fri, 6 Jan 2017 09:05:57 +0000 [thread overview]
Message-ID: <BL2PR08MB356C180B2FBF7C03466270497630@BL2PR08MB356.namprd08.prod.outlook.com> (raw)
In-Reply-To: <7F1BAD85ADEA444D97065A60D2E97EE5699A60C7@SHSMSX101.ccr.corp.intel.com>
Hi Feng,
I don’t understand why doorbell location should be updated too. If we don’t update UTRLBA & UTRLBAU for sending each UPIU packet, we have to extend the size of UTRD packet. Then we could avoid to create a new command buffer.
Best Regards
Haojian
From: Tian, Feng<mailto:feng.tian@intel.com>
Sent: 2017年1月6日 16:36
To: Haojian Zhuang<mailto:haojian.zhuang@linaro.org>; leif.lindholm@linaro.org<mailto:leif.lindholm@linaro.org>; ard.biesheuvel@linaro.org<mailto:ard.biesheuvel@linaro.org>; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
Cc: Tian, Feng<mailto:feng.tian@intel.com>
Subject: RE: [PATCH 4/9] Ufs: fix to set UTRLBA and UTRLBAU register
Hi, Haojian
If the UTRLBA & UTRLBAU gets changed like below, the doorbell location also should be updated. So I don't suggest to update them.
Thanks
Feng
-----Original Message-----
From: Haojian Zhuang [mailto:haojian.zhuang@linaro.org]
Sent: Friday, January 6, 2017 2:52 PM
To: Tian, Feng <feng.tian@intel.com>; leif.lindholm@linaro.org; ard.biesheuvel@linaro.org; edk2-devel@lists.01.org
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Subject: [PATCH 4/9] Ufs: fix to set UTRLBA and UTRLBAU register
Although UfsInitTransferRequestList () assigns UTRLBA && UTRLBAU registers, UfsCreateScsiCommandDesc () creates a page of command buffer. It means that UTRLBA && UTRLBAU registers should be updated.
Always set UTRLBA && UTRLBAU registers before sending UPIU packet.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
index e556b62..5c256a9 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
@@ -937,6 +937,8 @@ UfsRwDeviceDesc (
if (EFI_ERROR (Status)) {
return Status;
}
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBA_OFFSET, (UINTN)Trd &
+ 0xffffffff);
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBAU_OFFSET, ((UINTN)Trd >> 32) &
+ 0xffffffff);
//
// Check the transfer request result.
@@ -1060,6 +1062,8 @@ UfsRwAttributes (
if (EFI_ERROR (Status)) {
return Status;
}
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBA_OFFSET, (UINTN)Trd &
+ 0xffffffff);
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBAU_OFFSET, ((UINTN)Trd >> 32) &
+ 0xffffffff);
//
// Check the transfer request result.
@@ -1184,6 +1188,8 @@ UfsRwFlags (
if (EFI_ERROR (Status)) {
return Status;
}
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBA_OFFSET, (UINTN)Trd &
+ 0xffffffff);
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBAU_OFFSET, ((UINTN)Trd >> 32) &
+ 0xffffffff);
//
// Check the transfer request result.
@@ -1351,6 +1357,8 @@ UfsExecNopCmds (
if (EFI_ERROR (Status)) {
return Status;
}
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBA_OFFSET, (UINTN)Trd &
+ 0xffffffff);
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBAU_OFFSET, ((UINTN)Trd >> 32) &
+ 0xffffffff);
//
// Check the transfer request result.
@@ -1473,6 +1481,8 @@ UfsExecScsiCmds (
if (EFI_ERROR (Status)) {
return Status;
}
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBA_OFFSET, (UINTN)TransReq->Trd &
+ 0xffffffff);
+ UfsMmioWrite32 (Private, UFS_HC_UTRLBAU_OFFSET, ((UINTN)TransReq->Trd
+ >> 32) & 0xffffffff);
TransReq->CmdDescSize = TransReq->Trd->PrdtO * sizeof (UINT32) + TransReq->Trd->PrdtL * sizeof (UTP_TR_PRD);
--
2.7.4
next prev parent reply other threads:[~2017-01-08 9:25 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-06 6:52 [PATCH 0/9] enhance UFS Haojian Zhuang
2017-01-06 6:52 ` [PATCH 1/9] Ufs: fix data direction checking Haojian Zhuang
2017-01-06 7:08 ` Tian, Feng
2017-01-06 8:33 ` Haojian Zhuang
2017-01-06 6:52 ` [PATCH 2/9] Ufs: fix to identify 32 bits address mode Haojian Zhuang
2017-01-06 7:10 ` Tian, Feng
2017-01-06 6:52 ` [PATCH 3/9] Ufs: fix the bit in UFS_HC_UTRLDBR_OFFSET register Haojian Zhuang
2017-01-06 7:18 ` Tian, Feng
2017-01-06 6:52 ` [PATCH 4/9] Ufs: fix to set UTRLBA and UTRLBAU register Haojian Zhuang
2017-01-06 8:36 ` Tian, Feng
2017-01-06 9:05 ` Haojian Zhuang [this message]
2017-01-09 1:25 ` Tian, Feng
2017-01-06 6:52 ` [PATCH 5/9] Ufs: fix to set PRDT length Haojian Zhuang
2017-01-06 6:52 ` [PATCH 6/9] Ufs: add PhyInit Haojian Zhuang
2017-01-06 7:27 ` Tian, Feng
2017-01-06 8:21 ` Haojian Zhuang
2017-01-06 8:44 ` Tian, Feng
2017-01-06 6:52 ` [PATCH 7/9] Ufs: fix initialize OCS value to 0x0F Haojian Zhuang
2017-01-06 7:26 ` Tian, Feng
2017-01-06 8:18 ` Haojian Zhuang
2017-01-06 6:52 ` [PATCH 8/9] Ufs: fix to add cache operation Haojian Zhuang
2017-01-06 8:42 ` Tian, Feng
2017-01-06 6:52 ` [PATCH 9/9] ScsiDisk: retry if device detected power failure Haojian Zhuang
2017-01-06 8:22 ` Tian, Feng
2017-01-06 8:31 ` Haojian Zhuang
-- strict thread matches above, loose matches on Subject: below --
2017-01-10 6:09 [PATCH 4/9] Ufs: fix to set UTRLBA and UTRLBAU register haojian.zhuang
2017-01-10 7:47 ` Tian, Feng
2017-01-10 9:52 ` Haojian Zhuang
2017-01-11 1:00 ` Tian, Feng
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