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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Heng Luo > -----Original Message----- > From: mikuback@linux.microsoft.com > Sent: Tuesday, August 3, 2021 10:39 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L ; Luo, Heng > Subject: [edk2-platforms][PATCH v5 14/46] TigerlakeOpenBoardPkg: Use > IntelSiliconPkg BIOS area and ucode PCDs >=20 > From: Michael Kubacki >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 >=20 > Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs = are > declared in IntelSiliconPkg.dec. >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Cc: Heng Luo > Signed-off-by: Michael Kubacki > Reviewed-by: Nate DeSimone > --- > Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf = | 8 > ++--- >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapIn > clude.fdf | 4 +-- > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf > | 38 ++++++++++---------- > 3 files changed, 25 insertions(+), 25 deletions(-) >=20 > diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf > index 66c8814c97bb..56da991ab544 100644 > --- a/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf > +++ b/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf > @@ -39,8 +39,8 @@ [Packages] > BoardModulePkg/BoardModulePkg.dec >=20 > [Pcd] > - gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CON= SUMES > - gSiPkgTokenSpaceGuid.PcdBiosSize ## CON= SUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## > CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CON= SUMES > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## > CONSUMES > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## > CONSUMES > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ## > CONSUMES @@ -61,8 +61,8 @@ [Pcd] > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## > CONSUMES > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## > CONSUMES > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## > CONSUMES > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## > CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## > CONSUMES > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CON= SUMES > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CON= SUMES > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## > CONSUMES > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMap= I > nclude.fdf > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMap= I > nclude.fdf > index b21ae6401f12..24e2a963ba64 100644 > --- > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMap= I > nclude.fdf > +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/Fla > +++ shMapInclude.fdf > @@ -37,8 +37,8 @@ > ## Build script checks the requirement. > SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset = =3D > 0x00800000 # Flash addr (0xFFC00000) > SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize = =3D > 0x00080000 # Keep 0x80000 or larger > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = =3D > 0x00880000 # Flash addr (0xFFC80000) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = =3D 0x00070000 > # Keep 0x70000 or larger, change MicrocodeFv.fdf in case that this value = change > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = =3D > 0x00880000 # Flash addr (0xFFC80000) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = =3D > 0x00070000 # Keep 0x70000 or larger, change MicrocodeFv.fdf in case that= this > value change > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = =3D > 0x008F0000 # Flash addr (0xFFC00000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = =3D > 0x00080000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = =3D > 0x00970000 # Flash addr (0xFFD70000) > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf > index c1fd2be6af54..e3b2f048524c 100644 > --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf > +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fd > +++ f > @@ -29,8 +29,8 @@ [FD.TigerlakeURvp] > # assigned with PCD values. Instead, it uses the definitions for its var= iety, which > # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. > # > -BaseAddress =3D $(FLASH_BASE) | > gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the > FLASH Device. > -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size > in bytes of the FLASH Device > +BaseAddress =3D $(FLASH_BASE) | > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address = of > the FLASH Device. > +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size > #The size in bytes of the FLASH Device > ErasePolarity =3D 1 > BlockSize =3D $(FLASH_BLOCK_SIZE) > NumBlocks =3D $(FLASH_NUM_BLOCKS) > @@ -41,23 +41,23 @@ [FD.TigerlakeURvp] > # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, > because macro expression is not supported. > # So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase > to get the real CodeCache base address. > SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x1000 -SET > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset) > -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gSiPkgTokenSpaceGuid.PcdBiosSize > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + > +$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset) > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - > +$(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > +$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > +$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > +$(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gSiPkgTokenSpaceGuid.PcdBiosSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize >=20 > ################################################################# > ############### > # > # Following are lists of FD Region layout which correspond to the locati= ons of > different @@ -153,8 +153,8 @@ [FD.TigerlakeURvp] > gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|gBoardModul > eTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize > FV =3D FvFwBinaries >=20 > - > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.Pcd > FlashMicrocodeFvSize > - > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFl > ashMicrocodeFvSize > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconP > +kgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkg > +TokenSpaceGuid.PcdFlashMicrocodeFvSize > #Microcode > FV =3D FvMicrocode >=20 > -- > 2.28.0.windows.1