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boundary="_000_BN6PR05MB341110347374499FDA382CB0B97B0BN6PR05MB3411namp_" --_000_BN6PR05MB341110347374499FDA382CB0B97B0BN6PR05MB3411namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Andrei Warkentin ________________________________ From: Samer El-Haj-Mahmoud Sent: Monday, July 20, 2020 1:16 PM To: devel@edk2.groups.io Cc: Leif Lindholm ; Pete Batard ; Andrei W= arkentin ; Ard Biesheuvel Subject: [edk2-platform][PATCH v1 5/7] Platforms/RaspberryPi: SMBIOS Type 7= fixes Various fixes and enhancements for SMBIOS Type 7: - Break into 3 instances (L1 Instruction, L1 Data, and L2 cache) - Use correct values for RPi4 and RPi3 SoCs - Add Type 4 association with type 7 handles Cc: Leif Lindholm Cc: Pete Batard Cc: Andrei Warkentin Cc: Ard Biesheuvel Signed-off-by: Samer El-Haj-Mahmoud --- Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 146 += +++++++++++++++++-- 1 file changed, 133 insertions(+), 13 deletions(-) diff --git a/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosD= xe.c b/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index 4dcdec5615dc..4ee8ae6ebfc9 100644 --- a/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -291,12 +291,24 @@ CHAR8 *mProcessorInfoType4Strings[] =3D { /*********************************************************************** SMBIOS data definition TYPE7 Cache Information ************************************************************************/ -SMBIOS_TABLE_TYPE7 mCacheInfoType7 =3D { +SMBIOS_TABLE_TYPE7 mCacheInfoType7_L1I =3D { { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 }, 1, // SocketDesignation String - 0x018A, // Cache Configuration - 0x00FF, // Maximum Size 256k - 0x00FF, // Install Size 256k + 0x380, // Cache Configuration + //Cache Level :3 (L1) + //Cache Socketed :1 (Not Socketed) + //Reserved :1 + //Location :2 (Internal) + //Enabled/Disabled :1 (Enabled) + //Operational Mode :2 (Unknown) + //Reserved :6 +#if (RPI_MODEL =3D=3D 4) + 0x0030, // Maximum Size (RPi4: 48KB) + 0x0030, // Install Size (RPi4: 48KB) +#else + 0x0010, // Maximum Size (RPi3: 16KB) + 0x0010, // Install Size (RPi3: 16KB) +#endif { // Supported SRAM Type 0, //Other :1 0, //Unknown :1 @@ -317,16 +329,115 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7 =3D { 0, //Asynchronous :1 0 //Reserved :9 }, - 0, // Cache Speed unknown - CacheErrorMultiBit, // Error Correction Multi - CacheTypeUnknown, // System Cache Type - CacheAssociativity2Way // Associativity + 0, // Cache Speed unknown + CacheErrorParity, // Error Correction + CacheTypeInstruction, // System Cache Type + CacheAssociativity2Way // Associativity (RPi4 L1 Instruction cache i= s 3-way set associative, but SMBIOS spec does not define that) }; -CHAR8 *mCacheInfoType7Strings[] =3D { - "Cache1", +CHAR8 *mCacheInfoType7Strings_L1I[] =3D { + "L1 Instruction", NULL }; +SMBIOS_TABLE_TYPE7 mCacheInfoType7_L1D =3D { + { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 }, + 1, // SocketDesignation String + 0x180, // Cache Configuration + //Cache Level :3 (L1) + //Cache Socketed :1 (Not Socketed) + //Reserved :1 + //Location :2 (Internal) + //Enabled/Disabled :1 (Enabled) + //Operational Mode :2 (WB) + //Reserved :6 +#if (RPI_MODEL =3D=3D 4) + 0x0020, // Maximum Size (RPi4: 32KB) + 0x0020, // Install Size (RPi4: 32KB) +#else + 0x0010, // Maximum Size (RPi3: 16KB) + 0x0010, // Install Size (RPi3: 16KB) +#endif + { // Supported SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + { // Current SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction + CacheTypeData, // System Cache Type +#if (RPI_MODEL =3D=3D 4) + CacheAssociativity2Way // Associativity +#else + CacheAssociativity4Way // Associativity +#endif +}; +CHAR8 *mCacheInfoType7Strings_L1D[] =3D { + "L1 Data", + NULL +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_L2 =3D { + { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 }, + 1, // SocketDesignation String + 0x0181, // Cache Configuration + //Cache Level :3 (L2) + //Cache Socketed :1 (Not Socketed) + //Reserved :1 + //Location :2 (Internal) + //Enabled/Disabled :1 (Enabled) + //Operational Mode :2 (WB) + //Reserved :6 +#if (RPI_MODEL =3D=3D 4) + 0x0400, // Maximum Size (RPi4: 1MB) + 0x0400, // Install Size (RPi4: 1MB) +#else + 0x0200, // Maximum Size (RPi3: 512KB) + 0x0200, // Install Size (RPi3: 512KB) +#endif + { // Supported SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + { // Current SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction Multi + CacheTypeUnified, // System Cache Type + CacheAssociativity16Way // Associativity +}; +CHAR8 *mCacheInfoType7Strings_L2[] =3D { + "L2", + NULL +}; /*********************************************************************** SMBIOS data definition TYPE9 System Slot Information ************************************************************************/ @@ -846,7 +957,17 @@ CacheInfoUpdateSmbiosType7 ( VOID ) { - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7, mCacheInfoTyp= e7Strings, NULL); + EFI_SMBIOS_HANDLE SmbiosHandle; + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L1I, mCacheInf= oType7Strings_L1I, NULL); + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L1D, mCacheInf= oType7Strings_L1D, &SmbiosHandle); + // Set Type4 L1CacheHandle to point to the newly added L1 Data Cache + mProcessorInfoType4.L1CacheHandle =3D (UINT16) SmbiosHandle; + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L2, mCacheInfo= Type7Strings_L2, &SmbiosHandle); + // Set Type4 L2CacheHandle to point to the newly added L2 Cache + mProcessorInfoType4.L2CacheHandle =3D (UINT16) SmbiosHandle; } /*********************************************************************** @@ -972,11 +1093,10 @@ PlatformSmbiosDriverEntryPoint ( BoardInfoUpdateSmbiosType2 (); + CacheInfoUpdateSmbiosType7 (); // Add Type 7 first to get Cache handle f= or use in Type 4 ProcessorInfoUpdateSmbiosType4 (4); //One example for creating and upd= ating - CacheInfoUpdateSmbiosType7 (); - SysSlotInfoUpdateSmbiosType9 (); OemStringsUpdateSmbiosType11 (); -- 2.17.1 --_000_BN6PR05MB341110347374499FDA382CB0B97B0BN6PR05MB3411namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Andrei Warken= tin <awarkentin@vmware.com>
From: Samer El-Haj-Mahmoud = <Samer.El-Haj-Mahmoud@arm.com>
Sent: Monday, July 20, 2020 1:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Leif Lindholm <leif@nuviainc.com>; Pete Batard <pete@ak= eo.ie>; Andrei Warkentin <awarkentin@vmware.com>; Ard Biesheuvel &= lt;ard.biesheuvel@arm.com>
Subject: [edk2-platform][PATCH v1 5/7] Platforms/RaspberryPi: SMBIOS= Type 7 fixes
 
Various fixes and enhancements for SMBIOS Type 7:<= br>  - Break into 3 instances (L1 Instruction, L1 Data, and L2 cache)
 - Use correct values for RPi4 and RPi3 SoCs
 - Add Type 4 association with type 7 handles

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com> ---
 Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | = 146 ++++++++++++++++++--
 1 file changed, 133 insertions(+), 13 deletions(-)

diff --git a/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosD= xe.c b/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index 4dcdec5615dc..4ee8ae6ebfc9 100644
--- a/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -291,12 +291,24 @@ CHAR8 *mProcessorInfoType4Strings[] =3D {
 /********************************************************************= ***
         SMBIOS data definition&nbs= p; TYPE7  Cache Information
 *********************************************************************= ***/
-SMBIOS_TABLE_TYPE7 mCacheInfoType7 =3D {
+SMBIOS_TABLE_TYPE7 mCacheInfoType7_L1I =3D {
   { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE= 7), 0 },
   1,          =             &nb= sp; // SocketDesignation String
-  0x018A,          =             &nb= sp;            =     // Cache Configuration
-  0x00FF,          =             &nb= sp;            =     // Maximum Size 256k
-  0x00FF,          =             &nb= sp;            =     // Install Size 256k
+  0x380,          &= nbsp;         // Cache Configuratio= n
+       //Cache Level    =     :3  (L1)
+       //Cache Socketed   &nb= sp; :1  (Not Socketed)
+       //Reserved    &nb= sp;      :1
+       //Location    &nb= sp;      :2  (Internal)
+       //Enabled/Disabled   :1&nbs= p; (Enabled)
+       //Operational Mode   :2&nbs= p; (Unknown)
+       //Reserved    &nb= sp;      :6
+#if (RPI_MODEL =3D=3D 4)
+  0x0030,          =          // Maximum Size (RPi4: 48K= B)
+  0x0030,          =          // Install Size (RPi4: 48K= B)
+#else
+  0x0010,          =          // Maximum Size (RPi3: 16K= B)
+  0x0010,          =          // Install Size (RPi3: 16K= B)
+#endif
   {          &= nbsp;           &nbs= p;  // Supported SRAM Type
     0,  //Other     &nbs= p;       :1
     0,  //Unknown     &n= bsp;     :1
@@ -317,16 +329,115 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7 =3D {
     0,  //Asynchronous    &nb= sp; :1
     0   //Reserved    &n= bsp;     :9
   },
-  0,           = ;            &n= bsp;            = ;        // Cache Speed unknown
-  CacheErrorMultiBit,        =    // Error Correction Multi
-  CacheTypeUnknown,        &n= bsp;            // S= ystem Cache Type
-  CacheAssociativity2Way        //= Associativity
+  0,           = ;             /= / Cache Speed unknown
+  CacheErrorParity,         /= / Error Correction
+  CacheTypeInstruction,     // System Cache Type<= br> +  CacheAssociativity2Way    // Associativity  (RP= i4 L1 Instruction cache is 3-way set associative, but SMBIOS spec does not = define that)
 };
-CHAR8  *mCacheInfoType7Strings[] =3D {
-  "Cache1",
+CHAR8  *mCacheInfoType7Strings_L1I[] =3D {
+  "L1 Instruction",
   NULL
 };
 
+SMBIOS_TABLE_TYPE7 mCacheInfoType7_L1D =3D {
+  { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0= },
+  1,           = ;             /= / SocketDesignation String
+  0x180,          &= nbsp;         // Cache Configuratio= n
+       //Cache Level    =     :3  (L1)
+       //Cache Socketed   &nb= sp; :1  (Not Socketed)
+       //Reserved    &nb= sp;      :1
+       //Location    &nb= sp;      :2  (Internal)
+       //Enabled/Disabled   :1&nbs= p; (Enabled)
+       //Operational Mode   :2&nbs= p; (WB)
+       //Reserved    &nb= sp;      :6
+#if (RPI_MODEL =3D=3D 4)
+  0x0020,          =          // Maximum Size (RPi4: 32K= B)
+  0x0020,          =          // Install Size (RPi4: 32K= B)
+#else
+  0x0010,          =          // Maximum Size (RPi3: 16K= B)
+  0x0010,          =          // Install Size (RPi3: 16K= B)
+#endif
+  {           =             &nb= sp; // Supported SRAM Type
+    0,  //Other      &nb= sp;      :1
+    0,  //Unknown      &= nbsp;    :1
+    0,  //NonBurst      =     :1
+    1,  //Burst      &nb= sp;      :1
+    0,  //PiplelineBurst    :1
+    1,  //Synchronous     &nb= sp; :1
+    0,  //Asynchronous      := 1
+    0   //Reserved     &= nbsp;    :9
+  },
+  {           =             &nb= sp; // Current SRAM Type
+    0,  //Other      &nb= sp;      :1
+    0,  //Unknown      &= nbsp;    :1
+    0,  //NonBurst      =     :1
+    1,  //Burst      &nb= sp;      :1
+    0,  //PiplelineBurst    :1
+    1,  //Synchronous     &nb= sp; :1
+    0,  //Asynchronous      := 1
+    0   //Reserved     &= nbsp;    :9
+  },
+  0,           = ;             /= / Cache Speed unknown
+  CacheErrorSingleBit,      // Error Correct= ion
+  CacheTypeData,         = ;   // System Cache Type
+#if (RPI_MODEL =3D=3D 4)
+  CacheAssociativity2Way    // Associativity
+#else
+  CacheAssociativity4Way    // Associativity
+#endif
+};
+CHAR8  *mCacheInfoType7Strings_L1D[] =3D {
+  "L1 Data",
+  NULL
+};
+
+SMBIOS_TABLE_TYPE7 mCacheInfoType7_L2 =3D {
+  { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0= },
+  1,           = ;             /= / SocketDesignation String
+  0x0181,          =          // Cache Configuration
+       //Cache Level    =     :3  (L2)
+       //Cache Socketed   &nb= sp; :1  (Not Socketed)
+       //Reserved    &nb= sp;      :1
+       //Location    &nb= sp;      :2  (Internal)
+       //Enabled/Disabled   :1&nbs= p; (Enabled)
+       //Operational Mode   :2&nbs= p; (WB)
+       //Reserved    &nb= sp;      :6
+#if (RPI_MODEL =3D=3D 4)
+  0x0400,          =          // Maximum Size (RPi4: 1MB= )
+  0x0400,          =          // Install Size (RPi4: 1MB= )
+#else
+  0x0200,          =          // Maximum Size (RPi3: 512= KB)
+  0x0200,          =          // Install Size (RPi3: 512= KB)
+#endif
+  {           =             &nb= sp; // Supported SRAM Type
+    0,  //Other      &nb= sp;      :1
+    0,  //Unknown      &= nbsp;    :1
+    0,  //NonBurst      =     :1
+    1,  //Burst      &nb= sp;      :1
+    0,  //PiplelineBurst    :1
+    1,  //Synchronous     &nb= sp; :1
+    0,  //Asynchronous      := 1
+    0   //Reserved     &= nbsp;    :9
+  },
+  {           =             &nb= sp; // Current SRAM Type
+    0,  //Other      &nb= sp;      :1
+    0,  //Unknown      &= nbsp;    :1
+    0,  //NonBurst      =     :1
+    1,  //Burst      &nb= sp;      :1
+    0,  //PiplelineBurst    :1
+    1,  //Synchronous     &nb= sp; :1
+    0,  //Asynchronous      := 1
+    0   //Reserved     &= nbsp;    :9
+  },
+  0,           = ;             /= / Cache Speed unknown
+  CacheErrorSingleBit,      // Error Correct= ion Multi
+  CacheTypeUnified,         /= / System Cache Type
+  CacheAssociativity16Way   // Associativity
+};
+CHAR8  *mCacheInfoType7Strings_L2[] =3D {
+  "L2",
+  NULL
+};
 /********************************************************************= ***
         SMBIOS data definition&nbs= p; TYPE9  System Slot Information
 *********************************************************************= ***/
@@ -846,7 +957,17 @@ CacheInfoUpdateSmbiosType7 (
   VOID
   )
 {
-  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7, mCac= heInfoType7Strings, NULL);
+  EFI_SMBIOS_HANDLE SmbiosHandle;
+
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L1I, = mCacheInfoType7Strings_L1I, NULL);
+
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L1D, = mCacheInfoType7Strings_L1D, &SmbiosHandle);
+  // Set Type4 L1CacheHandle to point to the newly added L1 Data Cach= e
+  mProcessorInfoType4.L1CacheHandle =3D (UINT16) SmbiosHandle;
+
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L2, m= CacheInfoType7Strings_L2, &SmbiosHandle);
+  // Set Type4 L2CacheHandle to point to the newly added L2 Cache
+  mProcessorInfoType4.L2CacheHandle =3D (UINT16) SmbiosHandle;
 }
 
 /********************************************************************= ***
@@ -972,11 +1093,10 @@ PlatformSmbiosDriverEntryPoint (
 
   BoardInfoUpdateSmbiosType2 ();
 
+  CacheInfoUpdateSmbiosType7 (); // Add Type 7 first to get Cache han= dle for use in Type 4
 
   ProcessorInfoUpdateSmbiosType4 (4);   //One example = for creating and updating
 
-  CacheInfoUpdateSmbiosType7 ();
-
   SysSlotInfoUpdateSmbiosType9 ();
 
   OemStringsUpdateSmbiosType11 ();
--
2.17.1

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