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Thu, 4 Feb 2021 03:56:39 +0000 From: "Nate DeSimone" To: "Luo, Heng" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" Subject: Re: [PATCH 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and library instances Thread-Topic: [PATCH 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and library instances Thread-Index: AQHW+Drqz5ZT/k/5xEKNKyX7JRhAx6pHVj1A Date: Thu, 4 Feb 2021 03:56:39 +0000 Message-ID: References: <20210201013657.1833-1-heng.luo@intel.com> <20210201013657.1833-34-heng.luo@intel.com> In-Reply-To: <20210201013657.1833-34-heng.luo@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [50.53.190.176] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 64c451c1-e768-4b27-4279-08d8c8c0e03f x-ms-traffictypediagnostic: BN8PR11MB3843: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6430; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Heng, Please see comments inline. Thanks, Nate > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables > and library instances >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * SystemAgent/AcpiTables > * SystemAgent/Library/DxeSaPolicyLib > * SystemAgent/Library/PeiDxeSmmSaPlatformLib >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp > .asl | 252 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp > Common.asl | 289 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegComm > on.asl | 1344 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegRtd3.a > sl | 124 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl > | 26 ++++++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.a= sl > | 20 ++++++++++++++ > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.i= nf > | 22 +++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeS= a > PolicyLib.c | 264 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > + >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeS= a > PolicyLib.inf | 48 ++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeS= a > PolicyLibrary.h | 34 +++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatfor > mLib/PeiDxeSmmSaPlatformLib.inf | 32 ++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatfor > mLib/SaPlatformLibrary.c | 68 > +++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatfor > mLib/SaPlatformLibrary.h | 21 ++++++++++++++ > 13 files changed, 2544 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcie > Rp.asl > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcie > Rp.asl > new file mode 100644 > index 0000000000..0babf047ed > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcie > Rp.asl > @@ -0,0 +1,252 @@ > +/** @file >=20 > + This file contains the CPU PCIe Root Port configuration >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +External(LTRX) // CPU PCIe Root Port 0 Latency Tolerance Reporting Enabl= e >=20 > +External(LTRY) // CPU PCIe Root Port 1 Latency Tolerance Reporting Enabl= e >=20 > +External(LTRZ) // CPU PCIe Root Port 2 Latency Tolerance Reporting Enabl= e >=20 > +External(LTRW) // CPU PCIe Root Port 3 Latency Tolerance Reporting Enabl= e >=20 > +External(SMSL) // CPU PCIe Root Port Latency Tolerance Reporting Max > Snoop Latency >=20 > +External(SNSL) // CPU PCIe Root Port Latency Tolerance Reporting Max No > Snoop Latency >=20 > +External(PG0E) // CpuPcieRp0Enable 0: Disable; 1: Enable >=20 > +External(PG1E) // CpuPcieRp1Enable 0: Disable; 1: Enable >=20 > +External(PG2E) // CpuPcieRp2Enable 0: Disable; 1: Enable >=20 > +External(PG3E) // CpuPcieRp3Enable 0: Disable; 1: Enable >=20 > +External(\_SB.PC00.PEG0, DeviceObj) >=20 > +External(\_SB.PC00.PEG1, DeviceObj) >=20 > +External(\_SB.PC00.PEG2, DeviceObj) >=20 > +External(\_SB.PC00.PEG3, DeviceObj) >=20 > +External(\_SB.PC00.PEG0.PEGP, DeviceObj) >=20 > +External(\_SB.PC00.PEG1.PEGP, DeviceObj) >=20 > +External(\_SB.PC00.PEG2.PEGP, DeviceObj) >=20 > +External(\_SB.PC00.PEG3.PEGP, DeviceObj) >=20 > +External(\AR02) >=20 > +External(\PD02) >=20 > +External(\AR0A) >=20 > +External(\PD0A) >=20 > +External(\AR0B) >=20 > +External(\PD0B) >=20 > +External(\AR0C) >=20 > +External(\PD0C) >=20 > +External(VMDE) >=20 > +External(VMCP) >=20 > +External(MPGN) >=20 > +External(PBR1) >=20 > +External(PBR2) >=20 > +External(PBR3) >=20 > + >=20 > +Scope (\_SB.PC00.PEG0) { >=20 > + >=20 > + Name(SLOT, 0) // CPU PCIe root port index 0 corresponds to PEG60 (0/6/= 0) >=20 > + >=20 > + Method (_STA, 0x0, NotSerialized) { >=20 > + if(PG0E =3D=3D 1) { // If CPU PCIe RP0 enabled? >=20 > + Return(0x0F) >=20 > + } >=20 > + Return(0x00) >=20 > + } >=20 > + >=20 > + Name(LTEN, 0) >=20 > + Name(LMSL, 0) >=20 > + Name(LNSL, 0) >=20 > + >=20 > + Method(_INI) >=20 > + { >=20 > + Store (LTRX, LTEN) >=20 > + Store (SMSL, LMSL) >=20 > + Store (SNSL, LNSL) >=20 > + If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) { >=20 > + If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x8),0))) { >=20 > + Store (1, CPMV) >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + Method(_PRT,0) { >=20 > + If(PICM) { >=20 > + Return(AR02) >=20 > + } // APIC mode >=20 > + Return (PD02) // PIC Mode >=20 > + } // end _PRT >=20 > + >=20 > + Include("CpuPcieRpCommon.asl") >=20 > +} // PEG0 scope end >=20 > + >=20 > +Scope (\_SB.PC00.PEG1) { >=20 > + >=20 > + Name(SLOT, 1) // CPU PCIe root port index 1 corresponds to PEG10 (0/1/= 0) >=20 > + >=20 > + Method (_STA, 0x0, NotSerialized) { >=20 > + if(PG1E =3D=3D 1) { // If CPU PCIe RP1 enabled? >=20 > + Return(0x0F) >=20 > + } >=20 > + Return(0x00) >=20 > + } >=20 > + >=20 > + Name(LTEN, 0) >=20 > + Name(LMSL, 0) >=20 > + Name(LNSL, 0) >=20 > + >=20 > + Method(_INI) >=20 > + { >=20 > + Store (LTRY, LTEN) >=20 > + Store (SMSL, LMSL) >=20 > + Store (SNSL, LNSL) >=20 > + If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) { >=20 > + If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x1),0))) { >=20 > + Store (1, CPMV) >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + Method(_PRT,0) { >=20 > + If(PICM) { >=20 > + Return(AR0A) >=20 > + } // APIC mode >=20 > + Return (PD0A) // PIC Mode >=20 > + } // end _PRT >=20 > + >=20 > + Include("CpuPcieRpCommon.asl") >=20 > +} // PEG1 scope end >=20 > + >=20 > +Scope (\_SB.PC00.PEG2) { >=20 > + >=20 > + Name(SLOT, 2) // CPU PCIe root port index 2 corresponds to PEG11 (0/1/= 1) >=20 > + >=20 > + Method (_STA, 0x0, NotSerialized) { >=20 > + if(PG2E =3D=3D 1) { // If CPU PCIe RP2 enabled? >=20 > + Return(0x0F) >=20 > + } >=20 > + Return(0x00) >=20 > + } >=20 > + >=20 > + Name(LTEN, 0) >=20 > + Name(LMSL, 0) >=20 > + Name(LNSL, 0) >=20 > + >=20 > + Method(_INI) >=20 > + { >=20 > + Store (LTRZ, LTEN) >=20 > + Store (SMSL, LMSL) >=20 > + Store (SNSL, LNSL) >=20 > + If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) { >=20 > + If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x2),0))) { >=20 > + Store (1, CPMV) >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + Method(_PRT,0) { >=20 > + If(PICM) { >=20 > + Return(AR0B) >=20 > + } // APIC mode >=20 > + Return (PD0B) // PIC Mode >=20 > + } // end _PRT >=20 > + >=20 > + Include("CpuPcieRpCommon.asl") >=20 > +} // PEG2 scope end >=20 > + >=20 > +If (CondRefOf(\_SB.PC00.PEG3)) { >=20 > + Scope (\_SB.PC00.PEG3) { >=20 > + >=20 > + Name(SLOT, 3) // CPU PCIe root port index 3 corresponds to PEG12 > (0/1/2) >=20 > + >=20 > + Method (_STA, 0x0, NotSerialized) { >=20 > + if(PG3E =3D=3D 1) { // If CPU PCIe RP3 enabled? >=20 > + Return(0x0F) >=20 > + } >=20 > + Return(0x00) >=20 > + } >=20 > + >=20 > + Name(LTEN, 0) >=20 > + Name(LMSL, 0) >=20 > + Name(LNSL, 0) >=20 > + >=20 > + Method(_INI) >=20 > + { >=20 > + Store (LTRW, LTEN) >=20 > + Store (SMSL, LMSL) >=20 > + Store (SNSL, LNSL) >=20 > + If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) { >=20 > + If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x4),0))) { >=20 > + Store (1, CPMV) >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + Method(_PRT,0) { >=20 > + If(PICM) { >=20 > + Return(AR0C) >=20 > + } // APIC mode >=20 > + Return (PD0C) // PIC Mode >=20 > + } // end _PRT >=20 > + >=20 > + Include("CpuPcieRpCommon.asl") >=20 > + } // PEG3 scope end >=20 > +} >=20 > + >=20 > +Scope(\_SB.PC00.PEG0.PEGP) { >=20 > + Method(_PRW, 0) { >=20 > + Return(GPRW(0x69, 4)) // can wakeup from S4 state >=20 > + } >=20 > +} >=20 > + >=20 > + >=20 > +If (PBR1) { >=20 > + Scope(\_SB.PC00.PEG1.PEGP) { >=20 > + Method(_S0W, 0) { Return(4)} //D3cold is supported >=20 > + >=20 > + Device (PEGD) { >=20 > + Method(_S0W, 0) { Return(4)} //D3cold is supported >=20 > + Name(_ADR, 0x00000000) >=20 > + Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 > state >=20 > + } >=20 > + } // end "P.E.G. Port Slot x16" >=20 > +} >=20 > + >=20 > +Scope(\_SB.PC00.PEG1.PEGP) { >=20 > + Method(_PRW, 0) { >=20 > + Return(GPRW(0x69, 4)) // can wakeup from S4 state >=20 > + } >=20 > +} >=20 > + >=20 > + >=20 > +If (PBR2) { >=20 > + Scope(\_SB.PC00.PEG2.PEGP) { >=20 > + Method(_S0W, 0) { Return(4)} //D3cold is supported >=20 > + >=20 > + Device (PEGD) { >=20 > + Method(_S0W, 0) { Return(4)} //D3cold is supported >=20 > + Name(_ADR, 0x00000000) >=20 > + Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 > state >=20 > + } >=20 > + } // end "P.E.G. Port Slot 2x8" >=20 > +} >=20 > + >=20 > +Scope(\_SB.PC00.PEG2.PEGP) { >=20 > + Method(_PRW, 0) { >=20 > + Return(GPRW(0x69, 4)) // can wakeup from S4 state >=20 > + } >=20 > +} >=20 > + >=20 > +If (PBR3) { >=20 > + Scope(\_SB.PC00.PEG3.PEGP) { >=20 > + Method(_S0W, 0) { Return(4)} //D3cold is supported >=20 > + >=20 > + Device (PEGD) { >=20 > + Method(_S0W, 0) { Return(4)} //D3cold is supported >=20 > + Name(_ADR, 0x00000000) >=20 > + Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 > state >=20 > + } >=20 > + } // end "P.E.G. Port Slot 1x8 - 2x4" >=20 > +} >=20 > + >=20 > +If (CondRefOf(\_SB.PC00.PEG3)) { >=20 > + Scope(\_SB.PC00.PEG3.PEGP) { >=20 > + Method(_PRW, 0) { >=20 > + Return(GPRW(0x69, 4)) // can wakeup from S4 state >=20 > + } >=20 > + } >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcie > RpCommon.asl > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcie > RpCommon.asl > new file mode 100644 > index 0000000000..81f785dfc5 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcie > RpCommon.asl > @@ -0,0 +1,289 @@ > +/** @file >=20 > + This file contains the CPU PCIe Root Port configuration >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > + External(ECR1) >=20 > + External(GPRW, MethodObj) >=20 > + External(PICM) >=20 > + External(\_SB.PC00.PC2M, MethodObj) >=20 > + External(_ADR, IntObj) >=20 > + >=20 > + >=20 > + OperationRegion(PXCS,SystemMemory,\_SB.PC00.PC2M(_ADR),0x480) >=20 > + Field(PXCS, AnyAcc, NoLock, Preserve) >=20 > + { >=20 > + Offset(0), >=20 > + VDID, 32, >=20 > + Offset(0x50), // LCTL - Link Control Register >=20 > + L0SE, 1, // 0, L0s Entry Enabled >=20 > + , 3, >=20 > + LDIS, 1, >=20 > + , 3, >=20 > + Offset(0x52), // LSTS - Link Status Register >=20 > + , 13, >=20 > + LASX, 1, // 0, Link Active Status >=20 > + Offset(0x5A), // SLSTS[7:0] - Slot Status Register >=20 > + ABPX, 1, // 0, Attention Button Pressed >=20 > + , 2, >=20 > + PDCX, 1, // 3, Presence Detect Changed >=20 > + , 2, >=20 > + PDSX, 1, // 6, Presence Detect State >=20 > + , 1, >=20 > + Offset(0x60), // RSTS - Root Status Register >=20 > + , 16, >=20 > + PSPX, 1, // 16, PME Status >=20 > + Offset(0xA4), >=20 > + D3HT, 2, // Power State >=20 > + Offset(0xD8), // 0xD8, MPC - Miscellaneous Port Configuration Regist= er >=20 > + , 30, >=20 > + HPEX, 1, // 30, Hot Plug SCI Enable >=20 > + PMEX, 1, // 31, Power Management SCI Enable >=20 > + Offset(0xE0), // 0xE0, SPR - Scratch Pad Register >=20 > + , 0, >=20 > + SCB0, 1, // Sticky Scratch Pad Bit SCB0 >=20 > + Offset(0xE2), // 0xE2, RPPGEN - Root Port Power Gating Enable >=20 > + , 2, >=20 > + L23E, 1, // 2, L23_Rdy Entry Request (L23ER) >=20 > + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) >=20 > + Offset(0x324), // 0x324 - PCIEDBG >=20 > + , 3, >=20 > + LEDM, 1, // PCIEDBG.DMIL1EDM >=20 > + Offset(0x328), // 0x328 - PCIESTS1 >=20 > + , 24, >=20 > + LTSM, 8, >=20 > + } >=20 > + Field(PXCS,AnyAcc, NoLock, WriteAsZeros) >=20 > + { >=20 > + Offset(0xDC), // 0xDC, SMSCS - SMI/SCI Status Register >=20 > + , 30, >=20 > + HPSX, 1, // 30, Hot Plug SCI Status >=20 > + PMSX, 1 // 31, Power Management SCI Status >=20 > + } >=20 > + >=20 > + // >=20 > + // L23D method recovers link from L2 or L3 state. Used for RTD3 flows,= right > after endpoint is powered up and exits reset. >=20 > + // This flow is implemented in ASL because rootport registers used for > L2/L3 entry/exit >=20 > + // are proprietary and OS drivers don't know about them. >=20 > + // >=20 > + Method (L23D, 0, Serialized) { >=20 > + If(LNotEqual(SCB0,0x1)) { >=20 > + Return() >=20 > + } >=20 > + >=20 > + /// Set L23_Rdy to Detect Transition (L23R2DT) >=20 > + Store(1, L23R) >=20 > + Store(0, Local0) >=20 > + /// Wait for transition to Detect >=20 > + While(L23R) { >=20 > + If(Lgreater(Local0, 4)) >=20 > + { >=20 > + Break >=20 > + } >=20 > + Sleep(16) >=20 > + Increment(Local0) >=20 > + } >=20 > + Store(0,SCB0) >=20 > + >=20 > + /// Once in Detect, wait up to 124 ms for Link Active (typically hap= pens in > under 70ms) >=20 > + /// Worst case per PCIe spec from Detect to Link Active is: >=20 > + /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config > (24+2+2+2+2) >=20 > + Store(0, Local0) >=20 > + While(LEqual(LASX,0)) { >=20 > + If(Lgreater(Local0, 8)) >=20 > + { >=20 > + Break >=20 > + } >=20 > + Sleep(16) >=20 > + Increment(Local0) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // DL23 method puts link to L2 or L3 state. Used for RTD3 flows, befor= e > endpoint is powered down. >=20 > + // This flow is implemented in ASL because rootport registers used for > L2/L3 entry/exit >=20 > + // are proprietary and OS drivers don't know about them. >=20 > + // >=20 > + Method (DL23, 0, Serialized) { >=20 > + Store(1, L23E) >=20 > + Sleep(16) >=20 > + Store(0, Local0) >=20 > + While(L23E) { >=20 > + If(Lgreater(Local0, 4)) >=20 > + { >=20 > + Break >=20 > + } >=20 > + Sleep(16) >=20 > + Increment(Local0) >=20 > + } >=20 > + Store(1,SCB0) >=20 > + } >=20 > + >=20 > + Name(LTRV, Package(){0,0,0,0}) >=20 > + Name(CPMV, 0) // CPU Rp Mapped under VMD >=20 > + >=20 > + // >=20 > + // _DSM Device Specific Method >=20 > + // >=20 > + // Arg0: UUID Unique function identifier >=20 > + // Arg1: Integer Revision Level >=20 > + // Arg2: Integer Function Index (0 =3D Return Supported Functions) >=20 > + // Arg3: Package Parameters >=20 > + Method(_DSM, 4, Serialized) { >=20 > + // >=20 > + // Switch based on which unique function identifier was passed in >=20 > + // >=20 > + If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { >=20 > + // >=20 > + // _DSM Definitions for Latency Tolerance Reporting >=20 > + // >=20 > + // Arguments: >=20 > + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D >=20 > + // Arg1: Revision ID: 3 >=20 > + // Arg2: Function Index: 0, 6, 8, 9 >=20 > + // Arg3: Empty Package >=20 > + // >=20 > + // Switch by function index >=20 > + // >=20 > + Switch(ToInteger(Arg2)) { >=20 > + // >=20 > + // Function Index:0 >=20 > + // Standard query - A bitmask of functions supported >=20 > + // >=20 > + Case (0) { >=20 > + Name(OPTS,Buffer(2){0,0}) >=20 > + CreateBitField(OPTS,0,FUN0) >=20 > + CreateBitField(OPTS,6,FUN6) >=20 > + CreateBitField(OPTS,8,FUN8) >=20 > + CreateBitField(OPTS,9,FUN9) >=20 > + >=20 > + Store(1,FUN0) >=20 > + if(LEqual(LTEN,1)) { >=20 > + Store(1,Fun6) >=20 > + } >=20 > + >=20 > + If (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 >=20 > + If(CondRefOf(ECR1)) { >=20 > + if(LEqual(ECR1,1)){ >=20 > + if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision I= D: 3 >=20 > + Store(1,Fun8) >=20 > + Store(1,Fun9) >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + Return (OPTS) >=20 > + } >=20 > + >=20 > + // >=20 > + // Function Index: 6 >=20 > + // LTR Extended Capability Structure >=20 > + // >=20 > + Case(6) { >=20 > + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 >=20 > + Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0)) >=20 > + Store(And(LMSL,0x3FF), Index(LTRV, 1)) >=20 > + Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2)) >=20 > + Store(And(LNSL,0x3FF), Index(LTRV, 3)) >=20 > + Return (LTRV) >=20 > + } >=20 > + } >=20 > + Case(8) { //ECR ACPI additions for FW latency optimizations, DSM= for > Avoiding Power-On Reset Delay Duplication on Sx Resume >=20 > + If(CondRefOf(ECR1)) { >=20 > + if(LEqual(ECR1,1)){ >=20 > + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID= : 3 >=20 > + return (1) >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + Case(9) { //ECR ACPI additions for FW latency optimizations, DSM= for > Specifying Device Readiness Durations >=20 > + If(CondRefOf(ECR1)) { >=20 > + if(LEqual(ECR1,1)){ >=20 > + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID= : 3 >=20 > + return(Package(5){50000,Ones,Ones,50000,Ones}) >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } // End of switch(Arg2) >=20 > + } // End of if >=20 > + return (Buffer() {0x00}) >=20 > + } // End of _DSM >=20 > + >=20 > + Method(_PRW, 0) { >=20 > + Return(GPRW(0x69, 4)) // can wakeup from S4 state >=20 > + } >=20 > + >=20 > + Method(_PS0,0,Serialized) >=20 > + { >=20 > + If (LEqual(HPEX, 1)) { >=20 > + Store(0, HPEX) // Disable Hot Plug SCI >=20 > + Store(1, HPSX) // Clear Hot Plug SCI status >=20 > + } >=20 > + If (LEqual (PMEX, 1)) { >=20 > + Store(0, PMEX) // Disable Power Management SCI >=20 > + Store(1, PMSX) // Clear Power Management SCI status >=20 > + } >=20 > + } >=20 > + Method(_PS3,0,Serialized) >=20 > + { >=20 > + If (LEqual (HPEX, 0)) { >=20 > + Store(1, HPEX) // Enable Hot Plug SCI >=20 > + Store(1, HPSX) // Clear Hot Plug SCI status >=20 > + } >=20 > + If (LEqual(PMEX, 0)) { >=20 > + Store(1, PMEX) // Enable Power Management SCI >=20 > + Store(1, PMSX) // Clear Power Management SCI status >=20 > + } >=20 > + } >=20 > + >=20 > + Method (_DSD, 0) { >=20 > + Return ( >=20 > + Package () { >=20 > + ToUUID("FDF06FAD-F744-4451-BB64-ECD792215B10"), >=20 > + Package () { >=20 > + Package (2) {"FundamentalDeviceResetTriggeredOnD3ToD0", 1}, >=20 > + } >=20 > + } >=20 > + ) // End of Return () >=20 > + } >=20 > + >=20 > + // >=20 > + // PCI_EXP_STS Handler for PCIE Root Port >=20 > + // >=20 > + Method(HPME,0,Serialized) { >=20 > + If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exi= sts > and has PME SCI Status set... >=20 > + Store(1,PMSX) // clear rootport's PME SCI status >=20 > + Store(1,PSPX) // consume one pending PME status to prevent it from > blocking the queue >=20 > + Return(0x01) >=20 > + } >=20 > + Return(0x00) >=20 > + } >=20 > + >=20 > + // >=20 > + // Sub-Method of _L61 Hot-Plug event >=20 > + // _L61 event handler should invoke this method to support HotPlug wak= e > event from PEG RP >=20 > + // >=20 > + Method(HPEV,0,Serialized) { >=20 > + If(LAnd(LNotEqual(VDID,0xFFFFFFFF), HPSX)) { >=20 > + // Clear HotPlug SCI event status >=20 > + Store(1, HPSX) >=20 > + >=20 > + If(LEqual(PDCX, 1)) { >=20 > + // Clear Presence Detect Changed >=20 > + Store(1,PDCX) >=20 > + >=20 > + If(LEqual(PDSX, 0)) { >=20 > + // The PCI Express slot is empty, so disable L0s on hot unplug >=20 > + // >=20 > + Store(0,L0SE) >=20 > + } >=20 > + // Perform proper notification >=20 > + // to the OS. >=20 > + Notify(^,0) >=20 > + } >=20 > + } >=20 > + } >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegCom > mon.asl > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegCom > mon.asl > new file mode 100644 > index 0000000000..68b10309d4 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegCom > mon.asl > @@ -0,0 +1,1344 @@ > +/** @file >=20 > + This file contains the device definitions of the SystemAgent >=20 > + PCIE ACPI Reference Code. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +External(\_SB.ISME, MethodObj) >=20 > +External(\_SB.SHPO, MethodObj) >=20 > +External(\_SB.CAGS, MethodObj) >=20 > +External(\_SB.GGOV, MethodObj) >=20 > +External(\_SB.SGOV, MethodObj) >=20 > +External(\_SB.PC00.PEG0, DeviceObj) >=20 > +External(\_SB.PC00.PEG1, DeviceObj) >=20 > +External(\_SB.PC00.PEG2, DeviceObj) >=20 > +External(\_SB.PC00.PEG3, DeviceObj) >=20 > +External(\_SB.PC00.PEG0.PPRW, MethodObj) >=20 > +External(\_SB.PC00.PEG1.PPRW, MethodObj) >=20 > +External(\_SB.PC00.PEG2.PPRW, MethodObj) >=20 > +External(\_SB.PC00.PEG3.PPRW, MethodObj) >=20 > +External(\_SB.PC00.PC2M, MethodObj) >=20 > +External(P8XH, MethodObj) >=20 > +External(SPCO, MethodObj) >=20 > +External(PINI, MethodObj) // Platform specific PCIe root port initializa= tion >=20 > +External(PRES, MethodObj) >=20 > +External(GPRW, MethodObj) >=20 > +External(\SLOT) >=20 > +External(\P0WK) >=20 > +External(\P1WK) >=20 > +External(\P2WK) >=20 > +External(\P3WK) >=20 > +External(\XBAS) >=20 > +External(\SBN0) >=20 > +External(\SBN1) >=20 > +External(\SBN2) >=20 > +External(\SBN3) >=20 > +External(\EECP) >=20 > +External(\EEC1) >=20 > +External(\EEC2) >=20 > +External(\EEC3) >=20 > +External(\SGGP) >=20 > +External(\HRE0) >=20 > +External(\HRG0) >=20 > +External(\HRA0) >=20 > +External(\PWE0) >=20 > +External(\PWG0) >=20 > +External(\PWA0) >=20 > +External(\P1GP) >=20 > +External(\HRE1) >=20 > +External(\HRG1) >=20 > +External(\HRA1) >=20 > +External(\PWE1) >=20 > +External(\PWG1) >=20 > +External(\PWA1) >=20 > +External(\P2GP) >=20 > +External(\HRE2) >=20 > +External(\HRG2) >=20 > +External(\HRA2) >=20 > +External(\PWE2) >=20 > +External(\PWG2) >=20 > +External(\PWA2) >=20 > +External(\P3GP) >=20 > +External(\HRE3) >=20 > +External(\HRG3) >=20 > +External(\HRA3) >=20 > +External(\PWE3) >=20 > +External(\PWG3) >=20 > +External(\PWA3) >=20 > +External(\P0SC) >=20 > +External(\P1SC) >=20 > +External(\P2SC) >=20 > +External(\P3SC) >=20 > +External(\DLPW) >=20 > +External(\DLHR) >=20 > +External(\OBFX) >=20 > +External(\OBFY) >=20 > +External(\OBFZ) >=20 > +External(\OBFA) >=20 > +External(\OSYS) >=20 > + >=20 > +//GPE Event handling - Start >=20 > +Scope(\_GPE) { >=20 > + // >=20 > + // _L6F Method call for PEG0/1/2/3 ports to handle 2-tier RTD3 GPE eve= nts >=20 > + // >=20 > + Method(P0L6,0) >=20 > + { >=20 > + // PEG0 Device Wake Event >=20 > + If (\_SB.ISME(P0WK)) >=20 > + { >=20 > + \_SB.SHPO(P0WK, 1) // set gpio ownership to driver(0= =3DACPI mode, > 1=3DGPIO mode) >=20 > + Notify(\_SB.PC00.PEG0, 0x02) // device wake >=20 > + \_SB.CAGS(P0WK) // Clear GPE status bit for PEG0 WA= KE >=20 > + } >=20 > + } >=20 > + >=20 > + Method(P1L6,0) >=20 > + { >=20 > + // PEG1 Device Wake Event >=20 > + If (\_SB.ISME(P1WK)) >=20 > + { >=20 > + \_SB.SHPO(P1WK, 1) // set gpio ownership to driver(0= =3DACPI mode, > 1=3DGPIO mode) >=20 > + Notify(\_SB.PC00.PEG1, 0x02) // device wake >=20 > + \_SB.CAGS(P1WK) // Clear GPE status bit for PEG1 WA= KE >=20 > + } >=20 > + } >=20 > + >=20 > + Method(P2L6,0) >=20 > + { >=20 > + // PEG2 Device Wake Event >=20 > + If (\_SB.ISME(P2WK)) >=20 > + { >=20 > + \_SB.SHPO(P2WK, 1) // set gpio ownership to driver(0= =3DACPI mode, > 1=3DGPIO mode) >=20 > + Notify(\_SB.PC00.PEG2, 0x02) // device wake >=20 > + \_SB.CAGS(P2WK) // Clear GPE status bit for PEG2 WA= KE >=20 > + } >=20 > + } >=20 > + >=20 > + If (CondRefOf(\_SB.PC00.PEG3)) { >=20 > + Method(P3L6,0) >=20 > + { >=20 > + // PEG2 Device Wake Event >=20 > + If (\_SB.ISME(P3WK)) >=20 > + { >=20 > + \_SB.SHPO(P3WK, 1) // set gpio ownership to driver(0= =3DACPI > mode, 1=3DGPIO mode) >=20 > + Notify(\_SB.PC00.PEG3, 0x02) // device wake >=20 > + \_SB.CAGS(P3WK) // Clear GPE status bit for PEG2 = WAKE >=20 > + } >=20 > + } >=20 > + } >=20 > +} //Scope(\_GPE) >=20 > + >=20 > +If(LAnd((LEqual(HGMD,2)), (LEqual(HGST,1)))) { >=20 > +/// >=20 > +/// P.E.G. Root Port D6F0 >=20 > +/// >=20 > +Scope(\_SB.PC00.PEG0) { >=20 > + Name(WKEN, 0) >=20 > + >=20 > + PowerResource(PG00, 0, 0) { >=20 > + Name(_STA, One) >=20 > + Method(_ON, 0, Serialized) { >=20 > + If(LGreater(OSYS,2009)) { >=20 > + PGON(0) >=20 > + Store(One, _STA) >=20 > + } >=20 > + } >=20 > + Method(_OFF, 0, Serialized) { >=20 > + If(LGreater(OSYS,2009)) { >=20 > + PGOF(0) >=20 > + Store(Zero, _STA) >=20 > + } >=20 > + } >=20 > + } //End of PowerResource(PG00, 0, 0) >=20 > + >=20 > + Name(_PR0,Package(){PG00}) >=20 > + Name(_PR3,Package(){PG00}) >=20 > + >=20 > + /// >=20 > + /// This method is used to enable/disable wake from PEG60 (WKEN) >=20 > + /// >=20 > + Method(_DSW, 3) >=20 > + { >=20 > + If(Arg1) >=20 > + { >=20 > + Store(0, WKEN) /// If entering Sx, need to disable WAKE# fr= om > generating runtime PME >=20 > + } >=20 > + Else >=20 > + { /// If Staying in S0 >=20 > + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake >=20 > + { >=20 > + Store(1, WKEN) ///- Set PME >=20 > + } Else { >=20 > + Store(0, WKEN) ///- Disable runtime PME, either because stayi= ng in D0 > or disabling wake >=20 > + } >=20 > + } >=20 > + } // End _DSW >=20 > + >=20 > + /// >=20 > + /// This method is used to change the GPIO ownership back to ACPI and > will be called in PEG OFF Method >=20 > + /// >=20 > + Method(P0EW, 0) >=20 > + { >=20 > + If(WKEN) >=20 > + { >=20 > + If(LNotEqual(SGGP, 0x0)) >=20 > + { >=20 > + If(LEqual(SGGP, 0x1)) // GPIO mode >=20 > + { >=20 > + \_SB.SGOV(P0WK, 0x1) >=20 > + \_SB.SHPO(P0WK, 0x0) // set gpio ownership to ACPI(0=3DACP= I mode, > 1=3DGPIO mode) >=20 > + } >=20 > + } >=20 > + } >=20 > + } // End P0EW >=20 > + >=20 > + Method(_S0W, 0) { >=20 > + Return(4) //D3cold is supported >=20 > + } >=20 > +}// end "P.E.G. Root Port D6F0" >=20 > + >=20 > +/// >=20 > +/// P.E.G. Root Port D1F0 >=20 > +/// >=20 > +Scope(\_SB.PC00.PEG1) { >=20 > + Name(WKEN, 0) >=20 > + >=20 > + PowerResource(PG01, 0, 0) { >=20 > + Name(_STA, One) >=20 > + Method(_ON, 0, Serialized) { >=20 > + If(LGreater(OSYS,2009)) { >=20 > + PGON(1) >=20 > + Store(One, _STA) >=20 > + } >=20 > + } >=20 > + Method(_OFF, 0, Serialized) { >=20 > + If(LGreater(OSYS,2009)) { >=20 > + PGOF(1) >=20 > + Store(Zero, _STA) >=20 > + } >=20 > + } >=20 > + } //End of PowerResource(PG01, 0, 0) >=20 > + >=20 > + Name(_PR0,Package(){PG01}) >=20 > + Name(_PR3,Package(){PG01}) >=20 > + >=20 > + /// >=20 > + /// This method is used to enable/disable wake from PEG10 (WKEN) >=20 > + /// >=20 > + Method(_DSW, 3) >=20 > + { >=20 > + If(Arg1) >=20 > + { >=20 > + Store(0, WKEN) /// If entering Sx, need to disable WAKE# fr= om > generating runtime PME >=20 > + } >=20 > + Else >=20 > + { /// If Staying in S0 >=20 > + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake >=20 > + { >=20 > + Store(1, WKEN) ///- Set PME >=20 > + } Else { >=20 > + Store(0, WKEN) ///- Disable runtime PME, either because stayi= ng in D0 > or disabling wake >=20 > + } >=20 > + } >=20 > + } // End _DSW >=20 > + >=20 > + /// >=20 > + /// This method is used to change the GPIO ownership back to ACPI and > will be called in PEG OFF Method >=20 > + /// >=20 > + Method(P1EW, 0) >=20 > + { >=20 > + If(WKEN) >=20 > + { >=20 > + If(LNotEqual(P1GP, 0x0)) >=20 > + { >=20 > + If(LEqual(P1GP, 0x1)) // GPIO mode >=20 > + { >=20 > + \_SB.SGOV(P1WK, 0x1) >=20 > + \_SB.SHPO(P1WK, 0x0) // set gpio ownership to ACPI(0=3DACP= I mode, > 1=3DGPIO mode) >=20 > + } >=20 > + } >=20 > + } >=20 > + } // End P1EW >=20 > +}// end "P.E.G. Root Port D1F0" >=20 > + >=20 > +/// >=20 > +/// P.E.G. Root Port D1F1 >=20 > +/// >=20 > +Scope(\_SB.PC00.PEG2) { >=20 > + Name(WKEN, 0) >=20 > + >=20 > + PowerResource(PG02, 0, 0) { >=20 > + Name(_STA, One) >=20 > + Method(_ON, 0, Serialized) { >=20 > + If(LGreater(OSYS,2009)) { >=20 > + PGON(2) >=20 > + Store(One, _STA) >=20 > + } >=20 > + } >=20 > + Method(_OFF, 0, Serialized) { >=20 > + If(LGreater(OSYS,2009)) { >=20 > + PGOF(2) >=20 > + Store(Zero, _STA) >=20 > + } >=20 > + } >=20 > + } //End of PowerResource(PG02, 0, 0) >=20 > + >=20 > + Name(_PR0,Package(){PG02}) >=20 > + >=20 > + Name(_PR3,Package(){PG02}) >=20 > + >=20 > + /// >=20 > + /// This method is used to enable/disable wake from PEG11 (WKEN) >=20 > + /// >=20 > + Method(_DSW, 3) >=20 > + { >=20 > + If(Arg1) >=20 > + { >=20 > + Store(0, WKEN) /// If entering Sx, need to disable WAKE# fr= om > generating runtime PME >=20 > + } >=20 > + Else >=20 > + { /// If Staying in S0 >=20 > + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake >=20 > + { >=20 > + Store(1, WKEN) ///- Set PME >=20 > + } Else { >=20 > + Store(0, WKEN) ///- Disable runtime PME, either because stayi= ng in D0 > or disabling wake >=20 > + } >=20 > + } >=20 > + } // End _DSW >=20 > + >=20 > + /// >=20 > + /// This method is used to change the GPIO ownership back to ACPI and > will be called in PEG OFF Method >=20 > + /// >=20 > + Method(P2EW, 0) >=20 > + { >=20 > + If(WKEN) >=20 > + { >=20 > + If(LNotEqual(P2GP, 0x0)) >=20 > + { >=20 > + If(LEqual(P2GP, 0x1)) // GPIO mode >=20 > + { >=20 > + \_SB.SGOV(P2WK, 0x1) >=20 > + \_SB.SHPO(P2WK, 0x0) // set gpio ownership to ACPI(0=3DACP= I mode, > 1=3DGPIO mode) >=20 > + } >=20 > + } >=20 > + } >=20 > + } // End P2EW >=20 > +}// end "P.E.G. Root Port D1F1" >=20 > + >=20 > +/// >=20 > +/// P.E.G. Root Port D1F2 >=20 > +/// >=20 > +Scope(\_SB.PC00.PEG3) { >=20 > + Name(WKEN, 0) >=20 > + >=20 > + PowerResource(PG03, 0, 0) { >=20 > + Name(_STA, One) >=20 > + Method(_ON, 0, Serialized) { >=20 > + If(LGreater(OSYS,2009)) { >=20 > + PGON(3) >=20 > + Store(One, _STA) >=20 > + } >=20 > + } >=20 > + Method(_OFF, 0, Serialized) { >=20 > + If(LGreater(OSYS,2009)) { >=20 > + PGOF(3) >=20 > + Store(Zero, _STA) >=20 > + } >=20 > + } >=20 > + } //End of PowerResource(PG03, 0, 0) >=20 > + >=20 > + Name(_PR0,Package(){PG03}) >=20 > + Name(_PR3,Package(){PG03}) >=20 > + >=20 > + /// >=20 > + /// This method is used to enable/disable wake from PEG12 (WKEN) >=20 > + /// >=20 > + Method(_DSW, 3) >=20 > + { >=20 > + If(Arg1) >=20 > + { >=20 > + Store(0, WKEN) /// If entering Sx, need to disable WAKE# fr= om > generating runtime PME >=20 > + } >=20 > + Else >=20 > + { /// If Staying in S0 >=20 > + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake >=20 > + { >=20 > + Store(1, WKEN) ///- Set PME >=20 > + } Else { >=20 > + Store(0, WKEN) ///- Disable runtime PME, either because stayi= ng in D0 > or disabling wake >=20 > + } >=20 > + } >=20 > + } // End _DSW >=20 > + >=20 > + /// >=20 > + /// This method is used to change the GPIO ownership back to ACPI and > will be called in PEG OFF Method >=20 > + /// >=20 > + Method(P3EW, 0) >=20 > + { >=20 > + If(WKEN) >=20 > + { >=20 > + If(LNotEqual(P3GP, 0x0)) >=20 > + { >=20 > + If(LEqual(P3GP, 0x1)) // GPIO mode >=20 > + { >=20 > + \_SB.SGOV(P3WK, 0x1) >=20 > + \_SB.SHPO(P3WK, 0x0) // set gpio ownership to ACPI(0=3DACP= I mode, > 1=3DGPIO mode) >=20 > + } >=20 > + } >=20 > + } >=20 > + } // End P3EW >=20 > +}// end "P.E.G. Root Port D1F2" >=20 > + >=20 > +Scope (\_SB.PC00) { >=20 > + >=20 > + Name(IVID, 0xFFFF) //Invalid Vendor ID >=20 > + >=20 > + Name(PEBA, 0) //PCIE base address >=20 > + >=20 > + Name(PION, 0) //PEG index for ON Method >=20 > + Name(PIOF, 0) //PEG index for OFF Method >=20 > + >=20 > + Name(PBUS, 0) //PEG Rootport bus no >=20 > + Name(PDEV, 0) //PEG Rootport device no >=20 > + Name(PFUN, 0) //PEG Rootport function no >=20 > + >=20 > + Name(EBUS, 0) //Endpoint bus no >=20 > + Name(EDEV, 0) //Endpoint device no >=20 > + Name(EFN0, 0) //Endpoint function no 0 >=20 > + Name(EFN1, 1) //Endpoint function no 1 >=20 > + >=20 > + Name(LTRS, 0) >=20 > + Name(OBFS, 0) >=20 > + >=20 > + Name(DSOF, 0x06) //Device status PCI offset >=20 > + Name(CPOF, 0x34) //Capabilities pointer PCI offset >=20 > + Name(SBOF, 0x19) //PCI-2-PCI Secondary Bus number >=20 > + >=20 > + // PEG0 Endpoint variable to save/restore Link Capability, Link cont= rol, > Subsytem VendorId and Device Id >=20 > + Name (ELC0, 0x00000000) >=20 > + Name (ECP0, 0xffffffff) >=20 > + Name (H0VI, 0x0000) >=20 > + Name (H0DI, 0x0000) >=20 > + >=20 > + // PEG1 Endpoint variable to save/restore Link Capability, Link cont= rol, > Subsytem VendorId and Device Id >=20 > + Name (ELC1, 0x00000000) >=20 > + Name (ECP1, 0xffffffff) >=20 > + Name (H1VI, 0x0000) >=20 > + Name (H1DI, 0x0000) >=20 > + >=20 > + // PEG2 Endpoint variable to save/restore Link Capability, Link cont= rol, > Subsytem VendorId and Device Id >=20 > + Name (ELC2, 0x00000000) >=20 > + Name (ECP2, 0xffffffff) >=20 > + Name (H2VI, 0x0000) >=20 > + Name (H2DI, 0x0000) >=20 > + >=20 > + // PEG3 Endpoint variable to save/restore Link Capability, Link cont= rol, > Subsytem VendorId and Device Id >=20 > + Name (ELC3, 0x00000000) >=20 > + Name (ECP3, 0xffffffff) >=20 > + Name (H3VI, 0x0000) >=20 > + Name (H3DI, 0x0000) >=20 > + >=20 > + // PEG_AFELN[15:0]VMTX2_OFFSET variables >=20 > + Name(AFL0, 0) >=20 > + Name(AFL1, 0) >=20 > + Name(AFL2, 0) >=20 > + Name(AFL3, 0) >=20 > + Name(AFL4, 0) >=20 > + Name(AFL5, 0) >=20 > + Name(AFL6, 0) >=20 > + Name(AFL7, 0) >=20 > + Name(AFL8, 0) >=20 > + Name(AFL9, 0) >=20 > + Name(AFLA, 0) >=20 > + Name(AFLB, 0) >=20 > + Name(AFLC, 0) >=20 > + Name(AFLD, 0) >=20 > + Name(AFLE, 0) >=20 > + Name(AFLF, 0) >=20 > + >=20 > + // >=20 > + // Define a Memory Region for PEG60 root port that will allow access= to its >=20 > + // Register Block. >=20 > + // >=20 > + OperationRegion(OPG0, SystemMemory, Add(XBAS,0x30000), 0x1000) >=20 > + Field(OPG0, AnyAcc,NoLock,Preserve) >=20 > + { >=20 > + Offset(0), >=20 > + P0VI, 16, //Vendor ID PCI offset >=20 > + P0DI, 16, //Device ID PCI offset >=20 > + Offset(0x06), >=20 > + DSO0, 16, //Device status PCI offset >=20 > + Offset(0x34), >=20 > + CPO0, 8, //Capabilities pointer PCI offset >=20 > + Offset(0x0B0), >=20 > + , 4, >=20 > + P0LD, 1, //Link Disable >=20 > + Offset(0x11A), >=20 > + , 1, >=20 > + P0VC, 1, //VC0RSTS.VC0NP >=20 > + Offset(0x214), >=20 > + , 16, >=20 > + P0LS, 4, //PEGSTS.LKS >=20 > + Offset(0x248), >=20 > + , 7, >=20 > + Q0L2, 1, //L23_Rdy Entry Request for RTD3 >=20 > + Q0L0, 1, //L23 to Detect Transition for RTD3 >=20 > + Offset(0x504), >=20 > + HST0, 32, >=20 > + Offset(0x508), >=20 > + P0TR, 1, //TRNEN.TREN >=20 > + Offset(0xC74), >=20 > + P0LT, 4, //LTSSM_FSM_RESTORE.LTSSM_FSM_PS >=20 > + Offset(0xD0C), >=20 > + LRV0, 32, >=20 > + } >=20 > + >=20 > + // >=20 > + // Define a Memory Region for Endpoint on PEG60 root port >=20 > + // >=20 > + OperationRegion (PCS0, SystemMemory, Add(XBAS,ShiftLeft(SBN0,20)), > 0xF0) >=20 > + Field(PCS0, DWordAcc, Lock, Preserve) >=20 > + { >=20 > + Offset(0x0), >=20 > + D0VI, 16, >=20 > + Offset(0x2C), >=20 > + S0VI, 16, >=20 > + S0DI, 16, >=20 > + } >=20 > + >=20 > + OperationRegion(CAP0, SystemMemory, > Add(Add(XBAS,ShiftLeft(SBN0,20)),EECP),0x14) >=20 > + Field(CAP0,DWordAcc, NoLock,Preserve) >=20 > + { >=20 > + Offset(0x0C), // Link Capabilities Register >=20 > + LCP0, 32, // Link Capabilities Register D= ata >=20 > + Offset(0x10), >=20 > + LCT0, 16, // Link Control register >=20 > + } >=20 > + >=20 > + // >=20 > + // Define a Memory Region for PEG10 root port that will allow access= to its >=20 > + // Register Block. >=20 > + // >=20 > + OperationRegion(OPG1, SystemMemory, Add(XBAS,0x8000), 0x1000) >=20 > + Field(OPG1, AnyAcc,NoLock,Preserve) >=20 > + { >=20 > + Offset(0), >=20 > + P1VI, 16, //Vendor ID PCI offset >=20 > + P1DI, 16, //Device ID PCI offset >=20 > + Offset(0x06), >=20 > + DSO1, 16, //Device status PCI offset >=20 > + Offset(0x34), >=20 > + CPO1, 8, //Capabilities pointer PCI offset >=20 > + Offset(0x0B0), >=20 > + , 4, >=20 > + P1LD, 1, //Link Disable >=20 > + Offset(0x11A), >=20 > + , 1, >=20 > + P1VC, 1, //VC0RSTS.VC0NP >=20 > + Offset(0x214), >=20 > + , 16, >=20 > + P1LS, 4, //PEGSTS.LKS >=20 > + Offset(0x248), >=20 > + , 7, >=20 > + Q1L2, 1, //L23_Rdy Entry Request for RTD3 >=20 > + Q1L0, 1, //L23 to Detect Transition for RTD3 >=20 > + Offset(0x504), >=20 > + HST1, 32, >=20 > + Offset(0x508), >=20 > + P1TR, 1, //TRNEN.TREN >=20 > + Offset(0x70C), >=20 > + PA0V, 32, //PEG_AFELN0VMTX2_OFFSET >=20 > + Offset(0x71C), >=20 > + PA1V, 32, //PEG_AFELN1VMTX2_OFFSET >=20 > + Offset(0x72C), >=20 > + PA2V, 32, //PEG_AFELN2VMTX2_OFFSET >=20 > + Offset(0x73C), >=20 > + PA3V, 32, //PEG_AFELN3VMTX2_OFFSET >=20 > + Offset(0x74C), >=20 > + PA4V, 32, //PEG_AFELN4VMTX2_OFFSET >=20 > + Offset(0x75C), >=20 > + PA5V, 32, //PEG_AFELN5VMTX2_OFFSET >=20 > + Offset(0x76C), >=20 > + PA6V, 32, //PEG_AFELN6VMTX2_OFFSET >=20 > + Offset(0x77C), >=20 > + PA7V, 32, //PEG_AFELN7VMTX2_OFFSET >=20 > + Offset(0x78C), >=20 > + PA8V, 32, //PEG_AFELN8VMTX2_OFFSET >=20 > + Offset(0x79C), >=20 > + PA9V, 32, //PEG_AFELN9VMTX2_OFFSET >=20 > + Offset(0x7AC), >=20 > + PAAV, 32, //PEG_AFELNAVMTX2_OFFSET >=20 > + Offset(0x7BC), >=20 > + PABV, 32, //PEG_AFELNBVMTX2_OFFSET >=20 > + Offset(0x7CC), >=20 > + PACV, 32, //PEG_AFELNCVMTX2_OFFSET >=20 > + Offset(0x7DC), >=20 > + PADV, 32, //PEG_AFELNDVMTX2_OFFSET >=20 > + Offset(0x7EC), >=20 > + PAEV, 32, //PEG_AFELNEVMTX2_OFFSET >=20 > + Offset(0x7FC), >=20 > + PAFV, 32, //PEG_AFELNFVMTX2_OFFSET >=20 > + Offset(0x91C), >=20 > + , 31, >=20 > + BSP1, 1, >=20 > + Offset(0x93C), >=20 > + , 31, >=20 > + BSP2, 1, >=20 > + Offset(0x95C), >=20 > + , 31, >=20 > + BSP3, 1, >=20 > + Offset(0x97C), >=20 > + , 31, >=20 > + BSP4, 1, >=20 > + Offset(0x99C), >=20 > + , 31, >=20 > + BSP5, 1, >=20 > + Offset(0x9BC), >=20 > + , 31, >=20 > + BSP6, 1, >=20 > + Offset(0x9DC), >=20 > + , 31, >=20 > + BSP7, 1, >=20 > + Offset(0x9FC), >=20 > + , 31, >=20 > + BSP8, 1, >=20 > + Offset(0xC20), >=20 > + , 4, >=20 > + P1AP, 2, //AFEOVR.RXSQDETOVR >=20 > + Offset(0xC38), >=20 > + , 3, >=20 > + P1RM, 1, //CMNSPARE.PCUNOTL1 >=20 > + Offset(0xC3C), >=20 > + , 31, >=20 > + PRST, 1, >=20 > + Offset(0xC74), >=20 > + P1LT, 4, //LTSSM_FSM_RESTORE.LTSSM_FSM_PS >=20 > + Offset(0xD0C), >=20 > + LRV1, 32, >=20 > + } >=20 > + >=20 > + // >=20 > + // Define a Memory Region for Endpoint on PEG10 root port >=20 > + // >=20 > + OperationRegion (PCS1, SystemMemory, Add(XBAS,ShiftLeft(SBN1,20)), > 0xF0) >=20 > + Field(PCS0, DWordAcc, Lock, Preserve) >=20 > + { >=20 > + Offset(0x0), >=20 > + D1VI, 16, >=20 > + Offset(0x2C), >=20 > + S1VI, 16, >=20 > + S1DI, 16, >=20 > + } >=20 > + >=20 > + OperationRegion(CAP1, SystemMemory, > Add(Add(XBAS,ShiftLeft(SBN1,20)),EEC1),0x14) >=20 > + Field(CAP0,DWordAcc, NoLock,Preserve) >=20 > + { >=20 > + Offset(0x0C), // Link Capabilities Register >=20 > + LCP1, 32, // Link Capabilities Register D= ata >=20 > + Offset(0x10), >=20 > + LCT1, 16, // Link Control register >=20 > + } >=20 > + >=20 > + // >=20 > + // Define a Memory Region for PEG11 root port that will allow access= to its >=20 > + // Register Block. >=20 > + // >=20 > + OperationRegion(OPG2, SystemMemory, Add(XBAS,0x9000), 0x1000) >=20 > + Field(OPG2, AnyAcc,NoLock,Preserve) >=20 > + { >=20 > + Offset(0), >=20 > + P2VI, 16, //Vendor ID PCI offset >=20 > + P2DI, 16, //Device ID PCI offset >=20 > + Offset(0x06), >=20 > + DSO2, 16, //Device status PCI offset >=20 > + Offset(0x34), >=20 > + CPO2, 8, //Capabilities pointer PCI offset >=20 > + Offset(0x0B0), >=20 > + , 4, >=20 > + P2LD, 1, //Link Disable >=20 > + Offset(0x11A), >=20 > + , 1, >=20 > + P2VC, 1, //VC0RSTS.VC0NP >=20 > + Offset(0x214), >=20 > + , 16, >=20 > + P2LS, 4, //PEGSTS.LKS >=20 > + Offset(0x248), >=20 > + , 7, >=20 > + Q2L2, 1, //L23_Rdy Entry Request for RTD3 >=20 > + Q2L0, 1, //L23 to Detect Transition for RTD3 >=20 > + Offset(0x504), >=20 > + HST2, 32, >=20 > + Offset(0x508), >=20 > + P2TR, 1, //TRNEN.TREN >=20 > + Offset(0xC20), >=20 > + , 4, >=20 > + P2AP, 2, //AFEOVR.RXSQDETOVR >=20 > + Offset(0xC38), >=20 > + , 3, >=20 > + P2RM, 1, //CMNSPARE.PCUNOTL1 >=20 > + Offset(0xC74), >=20 > + P2LT, 4, //LTSSM_FSM_RESTORE.LTSSM_FSM_PS >=20 > + Offset(0xD0C), >=20 > + LRV2, 32, >=20 > + } >=20 > + >=20 > + // >=20 > + // Define a Memory Region for Endpoint on PEG11 root port >=20 > + // >=20 > + OperationRegion (PCS2, SystemMemory, Add(XBAS,ShiftLeft(SBN2,20)), > 0xF0) >=20 > + Field(PCS2, DWordAcc, Lock, Preserve) >=20 > + { >=20 > + Offset(0x0), >=20 > + D2VI, 16, >=20 > + Offset(0x2C), >=20 > + S2VI, 16, >=20 > + S2DI, 16, >=20 > + } >=20 > + >=20 > + OperationRegion(CAP2, SystemMemory, > Add(Add(XBAS,ShiftLeft(SBN2,20)),EEC2),0x14) >=20 > + Field(CAP2,DWordAcc, NoLock,Preserve) >=20 > + { >=20 > + Offset(0x0C), // Link Capabilities Register >=20 > + LCP2, 32, // Link Capabilities Register Data >=20 > + Offset(0x10), >=20 > + LCT2, 16, // Link Control register >=20 > + } >=20 > + >=20 > + >=20 > + // >=20 > + // Define a Memory Region for PEG12 root port that will allow access= to its >=20 > + // Register Block. >=20 > + // >=20 > + OperationRegion(OPG3, SystemMemory, Add(XBAS,0xA000), 0x1000) >=20 > + Field(OPG3, AnyAcc,NoLock,Preserve) >=20 > + { >=20 > + Offset(0), >=20 > + P3VI, 16, //Vendor ID PCI offset >=20 > + P3DI, 16, //Device ID PCI offset >=20 > + Offset(0x06), >=20 > + DSO3, 16, //Device status PCI offset >=20 > + Offset(0x34), >=20 > + CPO3, 8, //Capabilities pointer PCI offset >=20 > + Offset(0x0B0), >=20 > + , 4, >=20 > + P3LD, 1, //Link Disable >=20 > + Offset(0x11A), >=20 > + , 1, >=20 > + P3VC, 1, //VC0RSTS.VC0NP >=20 > + Offset(0x214), >=20 > + , 16, >=20 > + P3LS, 4, //PEGSTS.LKS >=20 > + Offset(0x248), >=20 > + , 7, >=20 > + Q3L2, 1, //L23_Rdy Entry Request for RTD3 >=20 > + Q3L0, 1, //L23 to Detect Transition for RTD3 >=20 > + Offset(0x504), >=20 > + HST3, 32, >=20 > + Offset(0x508), >=20 > + P3TR, 1, //TRNEN.TREN >=20 > + Offset(0xC20), >=20 > + , 4, >=20 > + P3AP, 2, //AFEOVR.RXSQDETOVR >=20 > + Offset(0xC38), >=20 > + , 3, >=20 > + P3RM, 1, //CMNSPARE.PCUNOTL1 >=20 > + Offset(0xC74), >=20 > + P3LT, 4, //LTSSM_FSM_RESTORE.LTSSM_FSM_PS >=20 > + Offset(0xD0C), >=20 > + LRV3, 32, >=20 > + } >=20 > + >=20 > + // >=20 > + // Define a Memory Region for Endpoint on PEG2 root port >=20 > + // >=20 > + OperationRegion (PCS3, SystemMemory, Add(XBAS,ShiftLeft(SBN3,20)), > 0xF0) >=20 > + Field(PCS2, DWordAcc, Lock, Preserve) >=20 > + { >=20 > + Offset(0x0), >=20 > + D3VI, 16, >=20 > + Offset(0x2C), >=20 > + S3VI, 16, >=20 > + S3DI, 16, >=20 > + } >=20 > + >=20 > + OperationRegion(CAP3, SystemMemory, > Add(Add(XBAS,ShiftLeft(SBN3,20)),EEC3),0x14) >=20 > + Field(CAP3,DWordAcc, NoLock,Preserve) >=20 > + { >=20 > + Offset(0x0C), // Link Capabilities Register >=20 > + LCP3, 32, // Link Capabilities Register Data >=20 > + Offset(0x10), >=20 > + LCT3, 16, // Link Control register >=20 > + } >=20 > + >=20 > + // >=20 > + // Name: PGON >=20 > + // Description: Function to put the Pcie Endpoint in ON state >=20 > + // Input: Arg0 -> PEG index >=20 > + // Return: Nothing >=20 > + // >=20 > + Method(PGON,1,Serialized) >=20 > + { >=20 > + Store(Arg0, PION) >=20 > + >=20 > + // >=20 > + // Check for the GPIO support on PEG0/1/2/3 Configuration and Retu= rn if > it is not supported. >=20 > + // >=20 > + If (LEqual(PION, 0)) >=20 > + { >=20 > + If (LEqual(SGGP, 0x0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + } >=20 > + ElseIf (LEqual(PION, 1)) >=20 > + { >=20 > + If (LEqual(P1GP, 0x0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + } >=20 > + ElseIf (LEqual(PION, 2)) >=20 > + { >=20 > + If (LEqual(P2GP, 0x0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + } >=20 > + ElseIf (LEqual(PION, 3)) >=20 > + { >=20 > + If (LEqual(P3GP, 0x0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + } >=20 > + Store(\XBAS, PEBA) >=20 > + Store(GDEV(PIOF), PDEV) >=20 > + Store(GFUN(PIOF), PFUN) >=20 > + >=20 > + /// de-assert CLK_REQ MSK >=20 > + PGSC(Arg0, 1) >=20 > + >=20 > + If (LEqual(CCHK(PION, 1), 0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + >=20 > + //Power on the Endpoint >=20 > + GPPR(PION, 1) >=20 > + >=20 > + // Restore PEG Recipe before program L23R2DT >=20 > + //\_SB.PC00.PEG1.RAVR() >=20 > + >=20 > + // Enable link for RTD3 >=20 > + RTEN() >=20 > + >=20 > + // Re-store the DGPU Subsystem VendorID, DeviceID & Link control > register data >=20 > + If (LEqual(PION, 0)) >=20 > + { >=20 > + Store(H0VI, S0VI) >=20 > + Store(H0DI, S0DI) >=20 > + Or(And(ELC0,0x0043),And(LCT0,0xFFBC),LCT0) >=20 > + } >=20 > + ElseIf (LEqual(PION, 1)) >=20 > + { >=20 > + Store(H1VI, S1VI) >=20 > + Store(H1DI, S1DI) >=20 > + Or(And(ELC1,0x0043),And(LCT1,0xFFBC),LCT1) >=20 > + } >=20 > + ElseIf (LEqual(PION, 2)) >=20 > + { >=20 > + Store(H2VI, S2VI) >=20 > + Store(H2DI, S2DI) >=20 > + Or(And(ELC2,0x0043),And(LCT2,0xFFBC),LCT2) >=20 > + } >=20 > + ElseIf (LEqual(PION, 3)) >=20 > + { >=20 > + Store(H3VI, S3VI) >=20 > + Store(H3DI, S3DI) >=20 > + Or(And(ELC3,0x0043),And(LCT3,0xFFBC),LCT3) >=20 > + } >=20 > + Return () >=20 > + } // End of Method(PGON,1,Serialized) >=20 > + >=20 > + // >=20 > + // Name: PGOF >=20 > + // Description: Function to put the Pcie Endpoint in OFF state >=20 > + // Input: Arg0 -> PEG index >=20 > + // Return: Nothing >=20 > + // >=20 > + Method(PGOF,1,Serialized) >=20 > + { >=20 > + >=20 > + Store(Arg0, PIOF) >=20 > + // >=20 > + // Check for the GPIO support on PEG0/1/2 Configuration and Return= if it > is not supported. >=20 > + // >=20 > + If (LEqual(PIOF, 0)) >=20 > + { >=20 > + If (LEqual(SGGP, 0x0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + } >=20 > + ElseIf (LEqual(PIOF, 1)) >=20 > + { >=20 > + If (LEqual(P1GP, 0x0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + } >=20 > + ElseIf (LEqual(PIOF, 2)) >=20 > + { >=20 > + If (LEqual(P2GP, 0x0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + } >=20 > + ElseIf (LEqual(PIOF, 3)) >=20 > + { >=20 > + If (LEqual(P3GP, 0x0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + } >=20 > + >=20 > + Store(\XBAS, PEBA) >=20 > + Store(GDEV(PIOF), PDEV) >=20 > + Store(GFUN(PIOF), PFUN) >=20 > + >=20 > + If (LEqual(CCHK(PIOF, 0), 0)) >=20 > + { >=20 > + Return () >=20 > + } >=20 > + >=20 > + // Save Endpoint Link Control register, Subsystem VendorID & Devic= e ID, > Link capability Data >=20 > + If (LEqual(Arg0, 0)) //PEG60 >=20 > + { >=20 > + Store(LCT0, ELC0) >=20 > + Store(S0VI, H0VI) >=20 > + Store(S0DI, H0DI) >=20 > + Store(LCP0, ECP0) >=20 > + } >=20 > + ElseIf (LEqual(Arg0, 1)) //PEG10 >=20 > + { >=20 > + Store(LCT1, ELC1) >=20 > + Store(S1VI, H1VI) >=20 > + Store(S1DI, H1DI) >=20 > + Store(LCP1, ECP1) >=20 > + } >=20 > + ElseIf (LEqual(Arg0, 2)) //PEG11 >=20 > + { >=20 > + Store(LCT2, ELC2) >=20 > + Store(S2VI, H2VI) >=20 > + Store(S2DI, H2DI) >=20 > + Store(LCP2, ECP2) >=20 > + } >=20 > + ElseIf (LEqual(Arg0, 3)) //PEG12 >=20 > + { >=20 > + Store(LCT3, ELC3) >=20 > + Store(S3VI, H3VI) >=20 > + Store(S3DI, H3DI) >=20 > + Store(LCP3, ECP3) >=20 > + } >=20 > + >=20 > + //\_SB.PC00.PEG0.SAVR() >=20 > + >=20 > + // Put link in L2 >=20 > + RTDS() >=20 > + >=20 > + /// assert CLK_REQ MSK >=20 > + /// >=20 > + /// On RTD3 entry, BIOS will instruct the PMC to disable source cl= ocks. >=20 > + /// This is done through sending a PMC IPC command. >=20 > + /// >=20 > + PGSC(Arg0, 0) >=20 > + >=20 > + //Power-off the Endpoint >=20 > + GPPR(PIOF, 0) >=20 > + //Method to set Wake GPIO ownership from GPIO to ACPI for Device > Initiated RTD3 >=20 > + DIWK(PIOF) >=20 > + >=20 > + Return () >=20 > + } // End of Method(PGOF,1,Serialized) >=20 > + >=20 > + >=20 > + // >=20 > + // Name: GDEV >=20 > + // Description: Function to return the PEG device no for the given P= EG > index >=20 > + // Input: Arg0 -> PEG index >=20 > + // Return: PEG device no for the given PEG index >=20 > + // >=20 > + Method(GDEV,1) >=20 > + { >=20 > + If(LEqual(Arg0, 0)) >=20 > + { >=20 > + Store(0x6, Local0) //Device6-Function0 =3D 00110.000 >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 1)) >=20 > + { >=20 > + Store(0x1, Local0) //Device1-Function0 =3D 00001.000 >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 2)) >=20 > + { >=20 > + Store(0x1, Local0) //Device1-Function2 =3D 00001.001 >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 3)) >=20 > + { >=20 > + Store(0x1, Local0) //Device1-Function3 =3D 00001.010 >=20 > + } >=20 > + >=20 > + Return(Local0) >=20 > + } // End of Method(GDEV,1) >=20 > + >=20 > + // >=20 > + // Name: GFUN >=20 > + // Description: Function to return the PEG function no for the given= PEG > index >=20 > + // Input: Arg0 -> PEG index >=20 > + // Return: PEG function no for the given PEG index >=20 > + // >=20 > + Method(GFUN,1) >=20 > + { >=20 > + If(LEqual(Arg0, 0)) >=20 > + { >=20 > + Store(0x0, Local0) //Device6-Function0 =3D 00110.000 >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 1)) >=20 > + { >=20 > + Store(0x0, Local0) //Device1-Function0 =3D 00001.000 >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 2)) >=20 > + { >=20 > + Store(0x1, Local0) //Device1-Function1 =3D 00001.001 >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 2)) >=20 > + { >=20 > + Store(0x2, Local0) //Device1-Function2 =3D 00001.010 >=20 > + } >=20 > + >=20 > + Return(Local0) >=20 > + } // End of Method(GFUN,1) >=20 > + >=20 > + // >=20 > + // Name: CCHK >=20 > + // Description: Function to check whether _ON/_OFF sequence is allow= ed > to execute for the given PEG controller or not >=20 > + // Input: Arg0 -> PEG index >=20 > + // Arg1 -> 0 means _OFF sequence, 1 means _ON sequence >=20 > + // Return: 0 - Don't execute the flow, 1 - Execute the flow >=20 > + // >=20 > + Method(CCHK,2) >=20 > + { >=20 > + >=20 > + //Check for Referenced PEG controller is present or not >=20 > + If(LEqual(Arg0, 0)) >=20 > + { >=20 > + Store(P0VI, Local7) >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 1)) >=20 > + { >=20 > + Store(P1VI, Local7) >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 2)) >=20 > + { >=20 > + Store(P2VI, Local7) >=20 > + } >=20 > + ElseIf(LEqual(Arg0, 3)) >=20 > + { >=20 > + Store(P3VI, Local7) >=20 > + } >=20 > + >=20 > + If(LEqual(Local7, IVID)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + >=20 > + If(LNotEqual(Arg0, 1)) >=20 > + { >=20 > + //Check for PEG10 controller presence >=20 > + Store(P1VI, Local7) >=20 > + If(LEqual(Local7, IVID)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + >=20 > + //If Endpoint is not present[already disabled] before executing PG= OF > then don't call the PGOF method >=20 > + //If Endpoint is present[already enabled] before executing PGON th= en > don't call the PGON method >=20 > + If(LEqual(Arg1, 0)) >=20 > + { >=20 > + //_OFF sequence condition check >=20 > + If(LEqual(Arg0, 0)) >=20 > + { >=20 > + If(LEqual(SGPI(SGGP, PWE0, PWG0, PWA0), 0)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + If(LEqual(Arg0, 1)) >=20 > + { >=20 > + If(LEqual(SGPI(P1GP, PWE1, PWG1, PWA1), 0)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + If(LEqual(Arg0, 2)) >=20 > + { >=20 > + If(LEqual(SGPI(P2GP, PWE2, PWG2, PWA2), 0)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + If(LEqual(Arg0, 3)) >=20 > + { >=20 > + If(LEqual(SGPI(P3GP, PWE3, PWG3, PWA3), 0)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + } >=20 > + ElseIf(LEqual(Arg1, 1)) >=20 > + { >=20 > + //_ON sequence condition check >=20 > + If(LEqual(Arg0, 0)) >=20 > + { >=20 > + If(LEqual(SGPI(SGGP, PWE0, PWG0, PWA0), 1)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + If(LEqual(Arg0, 1)) >=20 > + { >=20 > + If(LEqual(SGPI(P1GP, PWE1, PWG1, PWA1), 1)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + If(LEqual(Arg0, 2)) >=20 > + { >=20 > + If(LEqual(SGPI(P2GP, PWE2, PWG2, PWA2), 1)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + If(LEqual(Arg0, 3)) >=20 > + { >=20 > + If(LEqual(SGPI(P3GP, PWE3, PWG3, PWA3), 1)) >=20 > + { >=20 > + Return(0) >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + Return(1) >=20 > + } >=20 > + >=20 > + >=20 > + // >=20 > + // Name: SGPI [PCIe GPIO Read] >=20 > + // Description: Function to Read from PCIe GPIO >=20 > + // Input: Arg0 -> Gpio Support >=20 > + // Arg1 -> Expander Number >=20 > + // Arg2 -> Gpio Number >=20 > + // Arg3 -> Active Information >=20 > + // Return: GPIO value >=20 > + // >=20 > + Method(SGPI, 4, Serialized) >=20 > + { >=20 > + If (LEqual(Arg0, 0x01)) >=20 > + { >=20 > + // >=20 > + // PCH based GPIO >=20 > + // >=20 > + If (CondRefOf(\_SB.GGOV)) >=20 > + { >=20 > + Store(\_SB.GGOV(Arg2), Local0) >=20 > + } >=20 > + } >=20 > + // >=20 > + // Invert if Active Low >=20 > + // >=20 > + If (LEqual(Arg3,0)) >=20 > + { >=20 > + Not(Local0, Local0) >=20 > + And (Local0, 0x01, Local0) >=20 > + } >=20 > + >=20 > + Return(Local0) >=20 > + }// End of Method(SGPI) >=20 > + >=20 > + // Name: PGSC [PEG port source clock control] >=20 > + // Description: Function to enable/disable PEG port source clocks >=20 > + // Input: Arg0 -> PEG index >=20 > + // Arg1 -> Enable/Disable Clock (0 =3D Disable, 1 =3D Enable) >=20 > + // Return: Nothing >=20 > + // >=20 > + >=20 > + Method(PGSC, 2, Serialized) >=20 > + { >=20 > + If(LEqual(Arg0, 0)) { // PEG0 >=20 > + Store (P0SC, Local0) >=20 > + } ElseIf(LEqual(Arg0, 1)) { // PEG1 >=20 > + Store (P1SC, Local0) >=20 > + } ElseIf(LEqual(Arg0, 2)) { // PEG2 >=20 > + Store (P2SC, Local0) >=20 > + } ElseIf(LEqual(Arg0, 3)) {// PEG3 >=20 > + Store (P3SC, Local0) >=20 > + } Else { >=20 > + Return() >=20 > + } >=20 > + >=20 > + SPCO (Local0, Arg1) >=20 > + }// End of Method(PGSC) >=20 > + >=20 > + // >=20 > + // Name: GPPR >=20 > + // Description: Function to do Endpoint ON/OFF using GPIOs >=20 > + // There are two GPIOs currently used to control Third = Party > Vendor[TPV] DGPU Endpoint devices: >=20 > + // (1) DGPU_PWR_EN [used for Power control] >=20 > + // (2) DGPU_HOLD_RST[used for Reset control] >=20 > + // Input: Arg0 -> PEG index >=20 > + // Arg1 -> 0 means _OFF sequence, 1 means _ON sequence >=20 > + // Return: Nothing >=20 > + // >=20 > + Method(GPPR,2) >=20 > + { >=20 > + >=20 > + If(LEqual(Arg1, 0)) >=20 > + { >=20 > + //_OFF sequence GPIO programming >=20 > + If(LEqual(Arg0, 0)) >=20 > + { >=20 > + SGPO(SGGP, HRE0, HRG0, HRA0, 1) // Assert PCIe0/dGPU_HOLD_RST# > (PERST#) >=20 > + //Sleep(DLHR) // As per the PCIe spec, Wai= t for 'given'ms > after Assert the Reset >=20 > + SGPO(SGGP, PWE0, PWG0, PWA0, 0) // Deassert > PCIe0/dGPU_PWR_EN# >=20 > + } >=20 > + >=20 > + If(LEqual(Arg0, 1)) >=20 > + { >=20 > + SGPO(P1GP, HRE1, HRG1, HRA1, 1) // Assert PCIe1_HOLD_RST# > (PERST#) >=20 > + //Sleep(DLHR) // As per the PCIe spec, Wai= t for 'given'ms > after Assert the Reset >=20 > + SGPO(P1GP, PWE1, PWG1, PWA1, 0) // Deassert PCIe1_PWR_EN# >=20 > + } >=20 > + >=20 > + If(LEqual(Arg0, 2)) >=20 > + { >=20 > + SGPO(P2GP, HRE2, HRG2, HRA2, 1) // Assert PCIe2_HOLD_RST# > (PERST#) >=20 > + //Sleep(DLHR) // As per the PCIe spec, Wai= t for 'given'ms > after Assert the Reset >=20 > + SGPO(P2GP, PWE2, PWG2, PWA2, 0) // Deassert PCIe2_PWR_EN# >=20 > + } >=20 > + >=20 > + If(LEqual(Arg0, 3)) >=20 > + { >=20 > + SGPO(P3GP, HRE3, HRG3, HRA3, 1) // Assert PCIe3_HOLD_RST# > (PERST#) >=20 > + //Sleep(DLHR) // As per the PCIe spec, Wai= t for 'given'ms > after Assert the Reset >=20 > + SGPO(P3GP, PWE3, PWG3, PWA3, 0) // Deassert PCIe2_PWR_EN# >=20 > + } >=20 > + } >=20 > + ElseIf(LEqual(Arg1, 1)) >=20 > + { >=20 > + //_ON sequence GPIO programming >=20 > + If(LEqual(Arg0, 0)) >=20 > + { >=20 > + SGPO(SGGP, PWE0, PWG0, PWA0, 1) //Assert dGPU_PWR_EN# >=20 > + >=20 > + //Sleep(DLPW) // Wait for 'given'ms for power to get stable >=20 > + SGPO(SGGP, HRE0, HRG0, HRA0, 0) //Deassert dGPU_HOLD_RST# as > per the PCIe spec >=20 > + >=20 > + //Sleep(DLHR) // Wait for 'given'ms after Deassert >=20 > + } >=20 > + >=20 > + If(LEqual(Arg0, 1)) >=20 > + { >=20 > + SGPO(P1GP, PWE1, PWG1, PWA1, 1) //Assert dGPU_PWR_EN# >=20 > + >=20 > + //Sleep(DLPW) // Wait for 'given'ms for power to get stable >=20 > + SGPO(P1GP, HRE1, HRG1, HRA1, 0) //Deassert dGPU_HOLD_RST# as > per the PCIe spec >=20 > + >=20 > + //Sleep(DLHR) // Wait for 'given'ms after Deassert >=20 > + } >=20 > + >=20 > + If(LEqual(Arg0, 2)) >=20 > + { >=20 > + SGPO(P2GP, PWE2, PWG2, PWA2, 1) //Assert dGPU_PWR_EN# >=20 > + >=20 > + //Sleep(DLPW) // Wait for 'given'ms for power to get stable >=20 > + SGPO(P2GP, HRE2, HRG2, HRA2, 0) //Deassert dGPU_HOLD_RST# as > per the PCIe spec >=20 > + >=20 > + //Sleep(DLHR) // Wait for 'given'ms after Deassert >=20 > + } >=20 > + >=20 > + If(LEqual(Arg0, 3)) >=20 > + { >=20 > + SGPO(P3GP, PWE3, PWG3, PWA3, 1) //Assert dGPU_PWR_EN# >=20 > + >=20 > + //Sleep(DLPW) // Wait for 'given'ms for power to get stable >=20 > + SGPO(P3GP, HRE3, HRG3, HRA3, 0) //Deassert dGPU_HOLD_RST# as > per the PCIe spec >=20 > + >=20 > + //Sleep(DLHR) // Wait for 'given'ms after Deassert >=20 > + } >=20 > + } >=20 > + } // End of Method(GPPR,2) >=20 > + >=20 > + // >=20 > + // Name: SGPO [PCIe GPIO Write] >=20 > + // Description: Function to write into PCIe GPIO >=20 > + // Input: Arg0 -> Gpio Support >=20 > + // Arg1 -> Expander Number >=20 > + // Arg2 -> Gpio Number >=20 > + // Arg3 -> Active Information >=20 > + // Arg4 -> Value to write >=20 > + // Return: Nothing >=20 > + // >=20 > + >=20 > + Method(SGPO, 5, Serialized) >=20 > + { >=20 > + // >=20 > + // Invert if Active Low >=20 > + // >=20 > + If (LEqual(Arg3,0)) >=20 > + { >=20 > + Not(Arg4, Arg4) >=20 > + And(Arg4, 0x01, Arg4) >=20 > + } >=20 > + If (LEqual(Arg0, 0x01)) >=20 > + { >=20 > + // >=20 > + // PCH based GPIO >=20 > + // >=20 > + If (CondRefOf(\_SB.SGOV)) >=20 > + { >=20 > + \_SB.SGOV(Arg2, Arg4) >=20 > + } >=20 > + } >=20 > + } // End of Method(SGPO) >=20 > + >=20 > + // >=20 > + // Name: DIWK >=20 > + // Description: Function which set the GPIO ownership to ACPI for de= vice > initiated RTD3 >=20 > + // Input: PEG Index >=20 > + // Return: Nothing >=20 > + // >=20 > + Method(DIWK,1) >=20 > + { >=20 > + If (LEqual(Arg0, 0)) >=20 > + { >=20 > + \_SB.PC00.PEG0.P0EW() >=20 > + } >=20 > + ElseIf (LEqual(Arg0, 1)) >=20 > + { >=20 > + \_SB.PC00.PEG1.P1EW() >=20 > + } >=20 > + ElseIf (LEqual(Arg0, 2)) >=20 > + { >=20 > + \_SB.PC00.PEG2.P2EW() >=20 > + } >=20 > + ElseIf (LEqual(Arg0, 3)) >=20 > + { >=20 > + \_SB.PC00.PEG3.P3EW() >=20 > + } >=20 > + } >=20 > + }// End of Scope (\_SB.PC00) >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegRtd3 > .asl > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegRtd3 > .asl > new file mode 100644 > index 0000000000..b5d1a4e35e > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegRtd3 > .asl > @@ -0,0 +1,124 @@ > +/** @file >=20 > + This file contains the device definitions of the SystemAgent >=20 > + PCIE ACPI Reference Code. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +Scope (\_SB.PC00) { >=20 > + >=20 > + OperationRegion(PXCS,PCI_Config,0x00,0x480) >=20 > + Field(PXCS,AnyAcc, NoLock, Preserve) >=20 > + { >=20 > + Offset(0), >=20 > + VDID, 32, >=20 > + Offset(0x50), // LCTL - Link Control Register >=20 > + L0SE, 1, // 0, L0s Entry Enabled >=20 > + , 3, >=20 > + LDIS, 1, >=20 > + , 3, >=20 > + Offset(0x52), // LSTS - Link Status Register >=20 > + , 13, >=20 > + LASX, 1, // 0, Link Active Status >=20 > + Offset(0x5A), // SLSTS[7:0] - Slot Status Register >=20 > + ABPX, 1, // 0, Attention Button Pressed >=20 > + , 2, >=20 > + PDCX, 1, // 3, Presence Detect Changed >=20 > + , 2, >=20 > + PDSX, 1, // 6, Presence Detect State >=20 > + , 1, >=20 > + Offset(0x60), // RSTS - Root Status Register >=20 > + , 16, >=20 > + PSPX, 1, // 16, PME Status >=20 > + Offset(0xA4), >=20 > + D3HT, 2, // Power State >=20 > + Offset(0xD8), // 0xD8, MPC - Miscellaneous Port Configuration Regist= er >=20 > + , 30, >=20 > + HPEX, 1, // 30, Hot Plug SCI Enable >=20 > + PMEX, 1, // 31, Power Management SCI Enable >=20 > + Offset(0xE0), // 0xE0, SPR - Scratch Pad Register >=20 > + , 0, >=20 > + SCB0, 1, // Sticky Scratch Pad Bit SCB0 >=20 > + Offset(0xE2), // 0xE2, RPPGEN - Root Port Power Gating Enable >=20 > + , 2, >=20 > + L23E, 1, // 2, L23_Rdy Entry Request (L23ER) >=20 > + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) >=20 > + Offset(0x324), // 0x324 - PCIEDBG >=20 > + , 3, >=20 > + LEDM, 1, // PCIEDBG.DMIL1EDM >=20 > + Offset(0x328), // 0x328 - PCIESTS1 >=20 > + , 24, >=20 > + LTSM, 8, >=20 > + } >=20 > + Field(PXCS,AnyAcc, NoLock, WriteAsZeros) >=20 > + { >=20 > + Offset(0xDC), // 0xDC, SMSCS - SMI/SCI Status Register >=20 > + , 30, >=20 > + HPSX, 1, // 30, Hot Plug SCI Status >=20 > + PMSX, 1 // 31, Power Management SCI Status >=20 > + } >=20 > + >=20 > + // >=20 > + // Name: RTEN >=20 > + // Description: Function to Enable the link for RTD3 [RCTL.L22DT] >=20 > + // Input: PEG Index >=20 > + // Return: Nothing >=20 > + // >=20 > + Method(RTEN, 0, Serialized) >=20 > + { >=20 > + If (LNotEqual (SCB0,0x1)) { >=20 > + Return () >=20 > + } >=20 > + >=20 > + /// Set L23_Rdy to Detect Transition (L23R2DT) >=20 > + Store(1, L23R) >=20 > + Store(0, Local0) >=20 > + /// Wait for transition to Detect >=20 > + While(L23R) { >=20 > + If(Lgreater(Local0, 4)) >=20 > + { >=20 > + Break >=20 > + } >=20 > + Sleep(16) >=20 > + Increment(Local0) >=20 > + } >=20 > + Store(0,SCB0) >=20 > + >=20 > + /// Once in Detect, wait up to 124 ms for Link Active (typically h= appens in > under 70ms) >=20 > + /// Worst case per PCIe spec from Detect to Link Active is: >=20 > + /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Confi= g > (24+2+2+2+2) >=20 > + Store(0, Local0) >=20 > + While(LEqual(LASX,0)) { >=20 > + If(Lgreater(Local0, 8)) >=20 > + { >=20 > + Break >=20 > + } >=20 > + Sleep(16) >=20 > + Increment(Local0) >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Name: RTDS >=20 > + // Description: Function to Disable link for RTD3 [RCTL.L23ER] >=20 > + // Input: PEG Index >=20 > + // Return: Nothing >=20 > + // >=20 > + Method(RTDS, 0, Serialized) >=20 > + { >=20 > + Store(1, L23E) >=20 > + Sleep(16) >=20 > + Store(0, Local0) >=20 > + While(L23E) { >=20 > + If(Lgreater(Local0, 4)) >=20 > + { >=20 > + Break >=20 > + } >=20 > + Sleep(16) >=20 > + Increment(Local0) >=20 > + } >=20 > + Store(1,SCB0) >=20 > + } >=20 > + >=20 > +} // End of Scope (\_SB.PC00) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl > new file mode 100644 > index 0000000000..5228d9d753 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl > @@ -0,0 +1,26 @@ > +/** @file >=20 > + This file contains the device definition of the System Agent >=20 > + ACPI reference code. >=20 > + Currently defines the device objects for the >=20 > + System Agent PCI Express* ports (PEG), iGfx and other devices. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +External(\HGMD) >=20 > +External(\HGST) >=20 > +External(\_SB.PC00, DeviceObj) >=20 > +External(\_SB.PC00.GFX0, DeviceObj) >=20 > +External(\_SB.PC00.IPU0, DeviceObj) >=20 > +External(\_SB.PC00.B0D3, DeviceObj) >=20 > +External(\_SB.PC00.PCIC, MethodObj) >=20 > +External(\_SB.PC00.PCID, MethodObj) >=20 > +/// >=20 > +/// CPU PCIe Root Port >=20 > +/// >=20 > +include("CpuPcieRp.asl") >=20 > +include("PegCommon.asl") >=20 > +If(LAnd((LEqual(HGMD,2)), (LEqual(HGST,1)))) { >=20 > + include("PegRtd3.asl") >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.= a > sl > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.= a > sl > new file mode 100644 > index 0000000000..0494c659e0 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.= a > sl > @@ -0,0 +1,20 @@ > +/** @file >=20 > + This file contains the SystemAgent SSDT Table ASL code. >=20 > + It defines a Global NVS table which exchanges datas between OS >=20 > + and BIOS. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +DefinitionBlock ( >=20 > + "SaSsdt.aml", >=20 > + "SSDT", >=20 > + 0x02, >=20 > + "SaSsdt", >=20 > + "SaSsdt ", >=20 > + 0x3000 >=20 > + ) >=20 > +{ >=20 > + Include ("Sa.asl") >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.= i > nf > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.= i > nf > new file mode 100644 > index 0000000000..d0d1494b99 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.= i > nf > @@ -0,0 +1,22 @@ > +## @file >=20 > +# Component description file for the ACPI tables >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010005 >=20 > +BASE_NAME =3D SaSsdt >=20 > +FILE_GUID =3D ca89914d-2317-452e-b245-36c6fb77a9c6 >=20 > +MODULE_TYPE =3D USER_DEFINED >=20 > +VERSION_STRING =3D 1.0 >=20 > + >=20 > +[Sources] >=20 > + SaSsdt.asl >=20 > + >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLib.c > new file mode 100644 > index 0000000000..d33c20605a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLib.c > @@ -0,0 +1,264 @@ > +/** @file >=20 > + This file provide services for DXE phase policy default initialization >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include "DxeSaPolicyLibrary.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gMemoryDxeConfigGuid; >=20 > +extern EFI_GUID gPcieDxeConfigGuid; >=20 > + >=20 > +/** >=20 > + This function prints the SA DXE phase policy. >=20 > + >=20 > + @param[in] SaPolicy - SA DXE Policy protocol >=20 > +**/ >=20 > +VOID >=20 > +SaPrintPolicyProtocol ( >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + PCIE_DXE_CONFIG *PcieDxeConfig; >=20 > + MEMORY_DXE_CONFIG *MemoryDxeConfig; >=20 > + >=20 > + // >=20 > + // Get requisite IP Config Blocks which needs to be used here >=20 > + // >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gPcieDxeConfigGuid, (VO= ID > *)&PcieDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gMemoryDxeConfigGuid, > (VOID *)&MemoryDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + >=20 > + DEBUG_CODE_BEGIN (); >=20 > + INTN i; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print = BEGIN > -----------------\n")); >=20 > + DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy- > >TableHeader.Header.Revision)); >=20 > + ASSERT (SaPolicy->TableHeader.Header.Revision =3D=3D > SA_POLICY_PROTOCOL_REVISION); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "------------------------ > SA_MEMORY_CONFIGURATION -----------------\n")); >=20 > + //@todo: Matching the hardcode at lines 384. Need to be addressed. This is an old comment that is no longer relevant, please delete. >=20 > + DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", 4)); >=20 > + for (i =3D 0; i < 4; i++) { >=20 > + DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i])); >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "\n")); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, " ChannelASlotMap : %x\n", MemoryDxeConfig- > >ChannelASlotMap)); >=20 > + DEBUG ((DEBUG_INFO, " ChannelBSlotMap : %x\n", MemoryDxeConfig- > >ChannelBSlotMap)); >=20 > + DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n", MemoryDxeConfig- > >MrcTimeMeasure)); >=20 > + DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n", MemoryDxeConfig- > >MrcFastBoot)); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "------------------------ CPU_PCIE_CONFIGURATION > -----------------\n")); >=20 > + DEBUG ((DEBUG_INFO, " PegAspm[%d] :", SA_PEG_MAX_FUN)); >=20 > + for (i =3D 0; i < SA_PEG_MAX_FUN; i++) { >=20 > + DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegAspm[i])); >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "\n")); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :", SA_PEG_MAX_FUN)); >=20 > + for (i =3D 0; i < SA_PEG_MAX_FUN; i++) { >=20 > + DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegRootPortHPE[i])); >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "\n")); >=20 > + >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print = END -- > ---------------\n")); >=20 > + DEBUG_CODE_END (); >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + Load DXE Config block default for PCIe >=20 > + >=20 > + @param[in] ConfigBlockPointer Pointer to config block >=20 > +**/ >=20 > +VOID >=20 > +LoadPcieDxeDefault ( >=20 > + IN VOID *ConfigBlockPointer >=20 > + ) >=20 > +{ >=20 > + UINT8 Index; >=20 > + PCIE_DXE_CONFIG *PcieDxeConfig; >=20 > + >=20 > + PcieDxeConfig =3D ConfigBlockPointer; >=20 > + DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Name =3D %g\n", > &PcieDxeConfig->Header.GuidHob.Name)); >=20 > + DEBUG ((DEBUG_INFO, "PcieDxeConfig- > >Header.GuidHob.Header.HobLength =3D 0x%x\n", PcieDxeConfig- > >Header.GuidHob.Header.HobLength)); >=20 > + /// >=20 > + /// Initialize the PCIE Configuration >=20 > + /// PEG ASPM per port configuration. 4 PEG controllers i.e. 0,1,2,3 >=20 > + /// >=20 > + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { >=20 > + PcieDxeConfig->PegAspm[Index] =3D CpuPcieAspmAutoConfig; >=20 > + } >=20 > + >=20 > + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { >=20 > + PcieDxeConfig->PegPwrOpt[Index].LtrEnable =3D 1; >=20 > + PcieDxeConfig->PegPwrOpt[Index].LtrMaxSnoopLatency =3D > V_SA_LTR_MAX_SNOOP_LATENCY_VALUE; >=20 > + PcieDxeConfig->PegPwrOpt[Index].LtrMaxNoSnoopLatency =3D > V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE; >=20 > + PcieDxeConfig->PegPwrOpt[Index].ObffEnable =3D 1; >=20 > + } >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Load DXE Config block default >=20 > + >=20 > + @param[in] ConfigBlockPointer Pointer to config block >=20 > +**/ >=20 > +VOID >=20 > +LoadMemoryDxeDefault ( >=20 > + IN VOID *ConfigBlockPointer >=20 > + ) >=20 > +{ >=20 > + MEMORY_DXE_CONFIG *MemoryDxeConfig; >=20 > + >=20 > + MemoryDxeConfig =3D ConfigBlockPointer; >=20 > + DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Name =3D > %g\n", &MemoryDxeConfig->Header.GuidHob.Name)); >=20 > + DEBUG ((DEBUG_INFO, "MemoryDxeConfig- > >Header.GuidHob.Header.HobLength =3D 0x%x\n", MemoryDxeConfig- > >Header.GuidHob.Header.HobLength)); >=20 > + /// >=20 > + /// Initialize the Memory Configuration >=20 > + /// >=20 > + /// >=20 > + /// DIMM SMBus addresses info >=20 > + /// Refer to the SpdAddressTable[] mapping rule in DxeSaPolicyLibrary.= h >=20 > + /// >=20 > + MemoryDxeConfig->SpdAddressTable =3D AllocateZeroPool (sizeof (UINT8) > * 4); >=20 > + ASSERT (MemoryDxeConfig->SpdAddressTable !=3D NULL); >=20 > + if (MemoryDxeConfig->SpdAddressTable !=3D NULL) { >=20 > + MemoryDxeConfig->SpdAddressTable[0] =3D DIMM_SMB_SPD_P0C0D0; >=20 > + MemoryDxeConfig->SpdAddressTable[1] =3D DIMM_SMB_SPD_P0C0D1; >=20 > + MemoryDxeConfig->SpdAddressTable[2] =3D DIMM_SMB_SPD_P0C1D0; >=20 > + MemoryDxeConfig->SpdAddressTable[3] =3D DIMM_SMB_SPD_P0C1D1; >=20 > + } >=20 > + MemoryDxeConfig->ChannelASlotMap =3D 0x01; >=20 > + MemoryDxeConfig->ChannelBSlotMap =3D 0x01; >=20 > +} >=20 > + >=20 > +/** >=20 > + LoadSaDxeConfigBlockDefault - Initialize default settings for each SA = Config > block >=20 > + >=20 > + @param[in] ConfigBlockPointer The buffer pointer that will be > initialized as specific config block >=20 > + @param[in] BlockId Request to initialize defaults o= f specified > config block by given Block ID >=20 > + >=20 > + @retval EFI_SUCCESS The given buffer has contained t= he defaults > of requested config block >=20 > + @retval EFI_NOT_FOUND Block ID is not defined so no de= fault > Config block will be initialized >=20 > +**/ >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY > mSaDxeIpBlocks [] =3D { >=20 > + {&gPcieDxeConfigGuid, sizeof (PCIE_DXE_CONFIG), > PCIE_DXE_CONFIG_REVISION, LoadPcieDxeDefault}, >=20 > + {&gMemoryDxeConfigGuid, sizeof (MEMORY_DXE_CONFIG), > MEMORY_DXE_CONFIG_REVISION, LoadMemoryDxeDefault} >=20 > +}; >=20 > + >=20 > + >=20 > +/** >=20 > + CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy. >=20 > + It allocates and zero out buffer, and fills in the Intel default setti= ngs. >=20 > + >=20 > + @param[out] SaPolicy The pointer to get SA DXE Protocol= instance >=20 > + >=20 > + @retval EFI_SUCCESS The policy default is initialize= d. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CreateSaDxeConfigBlocks ( >=20 > + IN OUT SA_POLICY_PROTOCOL **SaPolicy >=20 > + ) >=20 > +{ >=20 > + UINT16 TotalBlockSize; >=20 > + EFI_STATUS Status; >=20 > + SA_POLICY_PROTOCOL *SaInitPolicy; >=20 > + UINT16 RequiredSize; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "SA Create Dxe Config Blocks\n")); >=20 > + >=20 > + SaInitPolicy =3D NULL; >=20 > + >=20 > + TotalBlockSize =3D GetComponentConfigBlockTotalSize > (&mSaDxeIpBlocks[0], sizeof (mSaDxeIpBlocks) / sizeof > (COMPONENT_BLOCK_ENTRY)); >=20 > + TotalBlockSize +=3D VtdGetConfigBlockTotalSizeDxe (); >=20 > + TotalBlockSize +=3D GraphicsGetConfigBlockTotalSizeDxe (); >=20 > + DEBUG ((DEBUG_INFO, "TotalBlockSize =3D 0x%x\n", TotalBlockSize)); >=20 > + >=20 > + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize; >=20 > + >=20 > + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *) &SaInitPolic= y); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // Initialize Policy Revision >=20 > + // >=20 > + SaInitPolicy->TableHeader.Header.Revision =3D > SA_POLICY_PROTOCOL_REVISION; >=20 > + // >=20 > + // Add config blocks. >=20 > + // >=20 > + Status =3D AddComponentConfigBlocks ((VOID *) SaInitPolicy, > &mSaDxeIpBlocks[0], sizeof (mSaDxeIpBlocks) / sizeof > (COMPONENT_BLOCK_ENTRY)); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // Vtd >=20 > + Status =3D VtdAddConfigBlocksDxe((VOID *) SaInitPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // Gfx >=20 > + Status =3D GraphicsAddConfigBlocksDxe ((VOID *) SaInitPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // Assignment for returning SaInitPolicy config block base address >=20 > + // >=20 > + *SaPolicy =3D SaInitPolicy; >=20 > + return Status; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + SaInstallPolicyProtocol installs SA Policy. >=20 > + While installed, RC assumes the Policy is ready and finalized. So plea= se > update and override >=20 > + any setting before calling this function. >=20 > + >=20 > + @param[in] ImageHandle Image handle of this driver. >=20 > + @param[in] SaPolicy The pointer to SA Policy Protoco= l instance >=20 > + >=20 > + @retval EFI_SUCCESS The policy is installed. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaInstallPolicyProtocol ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN SA_POLICY_PROTOCOL *SaPolicy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + /// >=20 > + /// Print SA DXE Policy >=20 > + /// >=20 > + SaPrintPolicyProtocol (SaPolicy); >=20 > + GraphicsDxePolicyPrint (SaPolicy); >=20 > + VtdPrintPolicyDxe (SaPolicy); >=20 > + >=20 > + /// >=20 > + /// Install protocol to to allow access to this Policy. >=20 > + /// >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &ImageHandle, >=20 > + &gSaPolicyProtocolGuid, >=20 > + SaPolicy, >=20 > + NULL >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLib.inf > new file mode 100644 > index 0000000000..8af3d09b80 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLib.inf > @@ -0,0 +1,48 @@ > +## @file >=20 > +# Component description file for the PeiSaPolicy library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D DxeSaPolicyLib >=20 > +FILE_GUID =3D B402A3A4-4B82-410E-B79C-5914880A05E7 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D DxeSaPolicyLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseMemoryLib >=20 > +UefiRuntimeServicesTableLib >=20 > +UefiBootServicesTableLib >=20 > +DebugLib >=20 > +PostCodeLib >=20 > +ConfigBlockLib >=20 > +HobLib >=20 > +DxeGraphicsPolicyLib >=20 > +DxeVtdPolicyLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +DxeSaPolicyLib.c >=20 > +DxeSaPolicyLibrary.h >=20 > + >=20 > + >=20 > +[Guids] >=20 > +gPcieDxeConfigGuid >=20 > +gMemoryDxeConfigGuid >=20 > + >=20 > + >=20 > +[Protocols] >=20 > +gSaPolicyProtocolGuid ## PRODUCES >=20 > + >=20 > +[Pcd] >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLibrary.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLibrary.h > new file mode 100644 > index 0000000000..d46dd44df3 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= e > SaPolicyLibrary.h > @@ -0,0 +1,34 @@ > +/** @file >=20 > + Header file for the DxeSaPolicy library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#ifndef _DXE_SA_POLICY_LIBRARY_H_ >=20 > +#define _DXE_SA_POLICY_LIBRARY_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include Remove this line >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define WORD_FIELD_VALID_BIT BIT15 >=20 > +#define MAX_PCIE_ASPM_OVERRIDE 500 >=20 > +#define MAX_PCIE_LTR_OVERRIDE 500 >=20 > +/// >=20 > +/// DIMM SMBus addresses >=20 > +/// >=20 > +#define DIMM_SMB_SPD_P0C0D0 0xA0 >=20 > +#define DIMM_SMB_SPD_P0C0D1 0xA2 >=20 > +#define DIMM_SMB_SPD_P0C1D0 0xA4 >=20 > +#define DIMM_SMB_SPD_P0C1D1 0xA6 >=20 > +#define DIMM_SMB_SPD_P0C0D2 0xA8 >=20 > +#define DIMM_SMB_SPD_P0C1D2 0xAA >=20 > + >=20 > +#endif // _DXE_SA_POLICY_LIBRARY_H_ >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/PeiDxeSmmSaPlatformLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/PeiDxeSmmSaPlatformLib.inf > new file mode 100644 > index 0000000000..0a632fc81a > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/PeiDxeSmmSaPlatformLib.inf > @@ -0,0 +1,32 @@ > +## @file >=20 > +# Component description file for SA Platform Lib >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmSaPlatformLib >=20 > +FILE_GUID =3D 9DB5ACB4-DB23-43AE-A283-2ABEF365CBE0 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D SaPlatformLib >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +BaseMemoryLib >=20 > +DebugLib >=20 > +IoLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +SaPlatformLibrary.h >=20 > +SaPlatformLibrary.c >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/SaPlatformLibrary.c > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/SaPlatformLibrary.c > new file mode 100644 > index 0000000000..42902d795c > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/SaPlatformLibrary.c > @@ -0,0 +1,68 @@ > +/** @file >=20 > + SA Platform Lib implementation. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include "SaPlatformLibrary.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > + >=20 > +/** >=20 > + Checks if SKU is Mobile >=20 > + >=20 > + @retval FALSE SKU is not Mobile >=20 > + @retval TRUE SKU is Mobile >=20 > +**/ >=20 > +BOOLEAN >=20 > +EFIAPI >=20 > +IsMobileSku ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT16 DeviceId; >=20 > + >=20 > + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS > (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, > R_SA_MC_DEVICE_ID)); >=20 > + if ( >=20 > + (DeviceId =3D=3D V_SA_DEVICE_ID_MB_ULT_1) || \ >=20 > + (DeviceId =3D=3D V_SA_DEVICE_ID_MB_ULT_2) || \ >=20 > + (DeviceId =3D=3D V_SA_DEVICE_ID_MB_ULX_1) || \ >=20 > + (DeviceId =3D=3D V_SA_DEVICE_ID_MB_ULX_2) \ >=20 > + ) { >=20 > + return TRUE; >=20 > + } >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Checks if SKU is Desktop >=20 > + >=20 > + @retval FALSE SKU is not Desktop >=20 > + @retval TRUE SKU is Desktop >=20 > +**/ >=20 > +BOOLEAN >=20 > +EFIAPI >=20 > +IsDesktopSku ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Checks if SKU is Server >=20 > + >=20 > + @retval FALSE SKU is not Server >=20 > + @retval TRUE SKU is Server >=20 > +**/ >=20 > +BOOLEAN >=20 > +EFIAPI >=20 > +IsServerSku ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/SaPlatformLibrary.h > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/SaPlatformLibrary.h > new file mode 100644 > index 0000000000..10513d0ea0 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf > ormLib/SaPlatformLibrary.h > @@ -0,0 +1,21 @@ > +/** @file >=20 > + Header file for SA Platform Lib implementation. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _SA_PLATFORM_LIBRARY_IMPLEMENTATION_H_ >=20 > +#define _SA_PLATFORM_LIBRARY_IMPLEMENTATION_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#endif >=20 > -- > 2.24.0.windows.2