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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Luo, Heng > Sent: Sunday, January 31, 2021 5:37 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 >=20 > Adds the following files: > * IpBlock/Espi/Library >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/E= sp > iLib.c | 469 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ >=20 > Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P= ei > DxeSmmEspiLib.inf | 38 ++++++++++++++++++++++++++++++++++++++ > 2 files changed, 507 insertions(+) >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib= /E > spiLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib= /E > spiLib.c > new file mode 100644 > index 0000000000..2d1928ce18 > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib= /E > spiLib.c > @@ -0,0 +1,469 @@ > +/** @file >=20 > + This file contains routines for eSPI >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define CHANNEL_RESET_TIMEOUT 100 ///< Channel reset timeout in us > after which to report error >=20 > +#define SLAVE_CHANNELS_MAX 7 ///< Max number of channels >=20 > + >=20 > +// >=20 > +// eSPI Slave registers >=20 > +// >=20 > +#define R_ESPI_SLAVE_GENCAP 0x08 ///< General Capabil= ities > and Configurations >=20 > +#define B_ESPI_SLAVE_GENCAP_SUPPCHAN 0xFF ///< Channels > supported bit mask >=20 > +#define R_ESPI_SLAVE_CHACAP_BASE 0x10 ///< Base address fr= om > which channel Cap and Conf registers start on slave >=20 > +#define S_ESPI_SLAVE_CHACAP_OFFSET 0x10 ///< Offset for each > channel from base >=20 > +#define B_ESPI_SLAVE_CHACAP_CHEN BIT0 ///< Slave Channel > enable bit >=20 > +#define B_ESPI_SLAVE_CHACAP_CHRDY BIT1 ///< Slave Channel > ready bit >=20 > + >=20 > +/** >=20 > + Checks if second slave capability is enabled >=20 > + >=20 > + @retval TRUE There's second slave >=20 > + @retval FALSE There's no second slave >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsEspiSecondSlaveSupported ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Checks in slave General Capabilities register if it supports channel w= ith > requested number >=20 > + >=20 > + @param[in] SlaveId Id of slave to check >=20 > + @param[in] ChannelNumber Number of channel of which to check >=20 > + >=20 > + @retval TRUE Channel with requested number is supported by slave > device >=20 > + @retval FALSE Channel with requested number is not supported by sl= ave > device >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsEspiSlaveChannelSupported ( >=20 > + UINT8 SlaveId, >=20 > + UINT8 ChannelNumber >=20 > + ) >=20 > +{ >=20 > + UINT32 Data32; >=20 > + UINT8 SupportedChannels; >=20 > + >=20 > + PchEspiSlaveGetConfig (SlaveId, R_ESPI_SLAVE_GENCAP, &Data32); >=20 > + SupportedChannels =3D (UINT8) (Data32 & > B_ESPI_SLAVE_GENCAP_SUPPCHAN); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "Slave %d supported channels 0x%4X\n", SlaveId, > SupportedChannels)); >=20 > + >=20 > + if (ChannelNumber > SLAVE_CHANNELS_MAX || !(SupportedChannels & > (BIT0 << ChannelNumber))) { >=20 > + // Incorrect channel number was specified. Either exceeded max or Sl= ave > doesn't support that channel. >=20 > + return FALSE; >=20 > + } >=20 > + >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Is eSPI enabled in strap. >=20 > + >=20 > + @retval TRUE Espi is enabled in strap >=20 > + @retval FALSE Espi is disabled in strap >=20 > +**/ >=20 > +BOOLEAN >=20 > +IsEspiEnabled ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) & > B_ESPI_PCR_CFG_VAL_ESPI_EN) !=3D 0; >=20 > +} >=20 > + >=20 > +/** >=20 > + eSPI helper function to clear slave configuration register status >=20 > + >=20 > + @retval EFI_SUCCESS Write to private config space succeed >=20 > + @retval others Read / Write failed >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +EspiClearScrs ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + PchPcrAndThenOr32 ( >=20 > + PID_ESPISPI, >=20 > + R_ESPI_PCR_SLV_CFG_REG_CTL, >=20 > + (UINT32) ~0, >=20 > + B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + eSPI helper function to poll slave configuration register enable for 0 >=20 > + and to check for slave configuration register status >=20 > + >=20 > + @retval EFI_SUCCESS Enable bit is zero and no error in status bi= ts >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS >=20 > + @retval others Read / Write to private config space failed >=20 > +**/ >=20 > +STATIC >=20 > +EFI_STATUS >=20 > +EspiPollScreAndCheckScrs ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT32 ScrStat; >=20 > + >=20 > + do { >=20 > + ScrStat =3D PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SLV_CFG_REG_CTL); >=20 > + } while ((ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE) !=3D 0); >=20 > + >=20 > + ScrStat =3D (ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS) >> > N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS; >=20 > + if (ScrStat !=3D V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR) { >=20 > + DEBUG ((DEBUG_ERROR, "eSPI slave config register status (error) is %= x > \n", ScrStat)); >=20 > + return EFI_DEVICE_ERROR; >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +typedef enum { >=20 > + EspiSlaveOperationConfigRead, >=20 > + EspiSlaveOperationConfigWrite, >=20 > + EspiSlaveOperationStatusRead, >=20 > + EspiSlaveOperationInBandReset >=20 > +} ESPI_SLAVE_OPERATION; >=20 > + >=20 > +/** >=20 > + Helper library to do all the operations regards to eSPI slave >=20 > + >=20 > + @param[in] SlaveId eSPI Slave ID >=20 > + @param[in] SlaveAddress Slave address to be put in > R_ESPI_PCR_SLV_CFG_REG_CTL[11:0] >=20 > + @param[in] SlaveOperation Based on ESPI_SLAVE_OPERATION >=20 > + @param[in,out] Data >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PCH_LP >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address > exceed maximum allowed >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address is > not DWord aligned >=20 > + @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to > 0x7FF has been locked >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +STATIC >=20 > +EFI_STATUS >=20 > +EspiSlaveOperationHelper ( >=20 > + IN UINT32 SlaveId, >=20 > + IN UINT32 SlaveAddress, >=20 > + IN ESPI_SLAVE_OPERATION SlaveOperation, >=20 > + IN OUT UINT32 *Data >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT32 Data32; >=20 > + >=20 > + // >=20 > + // Check the SlaveId is 0 or 1 >=20 > + // >=20 > + if (SlaveId >=3D PCH_MAX_ESPI_SLAVES) { >=20 > + DEBUG ((DEBUG_ERROR, "eSPI Slave ID of %d or more is not accepted > \n", PCH_MAX_ESPI_SLAVES)); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + // >=20 > + // Check if SlaveId 1 is used, it is not a PCH_LP >=20 > + // >=20 > + if (SlaveId =3D=3D 1) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + // >=20 > + // Check the address is not more then 0xFFF >=20 > + // >=20 > + if (SlaveAddress > B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA) { >=20 > + DEBUG ((DEBUG_ERROR, "eSPI Slave address must be less than 0x%x \n", > (B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA + 1))); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + // >=20 > + // Check the address is DWord aligned >=20 > + // >=20 > + if ((SlaveAddress & 0x3) !=3D 0) { >=20 > + DEBUG ((DEBUG_ERROR, "eSPI Slave address must be DWord aligned > \n")); >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + // >=20 > + // Check if write is allowed >=20 > + // >=20 > + if ((SlaveOperation =3D=3D EspiSlaveOperationConfigWrite) && >=20 > + (SlaveAddress <=3D 0x7FF)) { >=20 > + >=20 > + // >=20 > + // If the SLCRR is not set in corresponding slave, we will check the= lock bit >=20 > + // >=20 > + Data32 =3D PchPcrRead32 (PID_ESPISPI, (UINT16) > (R_ESPI_PCR_LNKERR_SLV0 + (SlaveId * S_ESPI_PCR_LNKERR_SLV0))); >=20 > + if ((Data32 & B_ESPI_PCR_LNKERR_SLV0_SLCRR) =3D=3D 0) { >=20 > + >=20 > + Data32 =3D PchPcrRead32 (PID_ESPISPI, (UINT16) > R_ESPI_PCR_SLV_CFG_REG_CTL); >=20 > + if ((Data32 & B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL) !=3D 0) { >=20 > + DEBUG ((DEBUG_ERROR, "eSPI Slave write to address range 0 to 0x7= FF > has been locked \n")); >=20 > + return EFI_ACCESS_DENIED; >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Input check done, now go through all the processes >=20 > + // >=20 > + EspiClearScrs (); >=20 > + >=20 > + if (SlaveOperation =3D=3D EspiSlaveOperationConfigWrite) { >=20 > + PchPcrWrite32 ( >=20 > + PID_ESPISPI, >=20 > + (UINT16) R_ESPI_PCR_SLV_CFG_REG_DATA, >=20 > + *Data >=20 > + ); >=20 > + } >=20 > + >=20 > + PchPcrAndThenOr32 ( >=20 > + PID_ESPISPI, >=20 > + (UINT16) R_ESPI_PCR_SLV_CFG_REG_CTL, >=20 > + (UINT32) ~(B_ESPI_PCR_SLV_CFG_REG_CTL_SID | > B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT | > B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA), >=20 > + (B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE | >=20 > + (SlaveId << N_ESPI_PCR_SLV_CFG_REG_CTL_SID) | >=20 > + (((UINT32) SlaveOperation) << N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT) | >=20 > + SlaveAddress >=20 > + ) >=20 > + ); >=20 > + >=20 > + Status =3D EspiPollScreAndCheckScrs (); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + if ((SlaveOperation =3D=3D EspiSlaveOperationConfigRead) || (SlaveOper= ation > =3D=3D EspiSlaveOperationStatusRead)) { >=20 > + Data32 =3D PchPcrRead32 ( >=20 > + PID_ESPISPI, >=20 > + (UINT16) R_ESPI_PCR_SLV_CFG_REG_DATA >=20 > + ); >=20 > + if (SlaveOperation =3D=3D EspiSlaveOperationStatusRead) { >=20 > + *Data =3D Data32 & 0xFFFF; >=20 > + } else { >=20 > + *Data =3D Data32; >=20 > + } >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get configuration from eSPI slave >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + @param[in] SlaveAddress Slave Configuration Register Address >=20 > + @param[out] OutData Configuration data read >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PCH_LP >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address > exceed maximum allowed >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address is > not DWord aligned >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveGetConfig ( >=20 > + IN UINT32 SlaveId, >=20 > + IN UINT32 SlaveAddress, >=20 > + OUT UINT32 *OutData >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // 1. Clear status from previous transaction by writing 111b to status= in > SCRS, PCR[eSPI] + 4000h [30:28] >=20 > + // 2. Program SLV_CFG_REG_CTL with the right value (Bit[31]=3D01, Bit > [20:19]=3D, Bit [17:16] =3D 00b, Bit[11:0] =3D . >=20 > + // 3. Poll the SCRE (PCR[eSPI] +4000h [31]) to be set back to 0 >=20 > + // 4. Check the transaction status in SCRS (bits [30:28]) >=20 > + // 5. Read SLV_CFG_REG_DATA. >=20 > + // >=20 > + return EspiSlaveOperationHelper (SlaveId, SlaveAddress, > EspiSlaveOperationConfigRead, OutData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Set eSPI slave configuration >=20 > + >=20 > + Note: A Set_Configuration must always be followed by a > Get_Configuration in order to ensure >=20 > + that the internal state of the eSPI-MC is consistent with the Slave's = register > settings. >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + @param[in] SlaveAddress Slave Configuration Register Address >=20 > + @param[in] InData Configuration data to write >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PCH_LP >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address > exceed maximum allowed >=20 > + @retval EFI_INVALID_PARAMETER Slave configuration register address is > not DWord aligned >=20 > + @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to > 0x7FF has been locked >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveSetConfig ( >=20 > + IN UINT32 SlaveId, >=20 > + IN UINT32 SlaveAddress, >=20 > + IN UINT32 InData >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT32 Data32; >=20 > + >=20 > + // >=20 > + // 1. Clear status from previous transaction by writing 111b to status= in > SCRS, PCR[eSPI] + 4000h [30:28] >=20 > + // 2. Program SLV_CFG_REG_DATA with the write value. >=20 > + // 3. Program SLV_CFG_REG_CTL with the right value (Bit[31]=3D01, Bit > [20:19]=3D, Bit [17:16] =3D 01b, Bit[11:0] =3D . >=20 > + // 4. Poll the SCRE (PCR[eSPI] +4000h [31]) to be set back to 0 >=20 > + // 5. Check the transaction status in SCRS (bits [30:28]) >=20 > + // >=20 > + Status =3D EspiSlaveOperationHelper (SlaveId, SlaveAddress, > EspiSlaveOperationConfigWrite, &InData); >=20 > + PchEspiSlaveGetConfig (SlaveId, SlaveAddress, &Data32); >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get status from eSPI slave >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + @param[out] OutData Configuration data read >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PCH_LP >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveGetStatus ( >=20 > + IN UINT32 SlaveId, >=20 > + OUT UINT16 *OutData >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT32 TempOutData; >=20 > + >=20 > + TempOutData =3D 0; >=20 > + >=20 > + // >=20 > + // 1. Clear status from previous transaction by writing 111b to status= in > SCRS, PCR[eSPI] + 4000h [30:28] >=20 > + // 2. Program SLV_CFG_REG_CTL with the right value (Bit[31]=3D01, Bit > [20:19]=3D, Bit [17:16] =3D 10b, Bit[11:0] =3D . >=20 > + // 3. Poll the SCRE (PCR[eSPI] +4000h [31]) to be set back to 0 >=20 > + // 4. Check the transaction status in SCRS (bits [30:28]) >=20 > + // 5. Read SLV_CFG_REG_DATA [15:0]. >=20 > + // >=20 > + Status =3D EspiSlaveOperationHelper (SlaveId, 0, > EspiSlaveOperationStatusRead, &TempOutData); >=20 > + *OutData =3D (UINT16) TempOutData; >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + eSPI slave in-band reset >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeed >=20 > + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 i= s > used in PCH_LP >=20 > + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of > operation >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveInBandReset ( >=20 > + IN UINT32 SlaveId >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // 1. Clear status from previous transaction by writing 111b to status= in > SCRS, PCR[eSPI] + 4000h [30:28] >=20 > + // 2. Program SLV_CFG_REG_CTL with the right value (Bit[31]=3D01, Bit > [20:19]=3D, Bit [17:16] =3D 11b). >=20 > + // 3. Poll the SCRE (PCR[eSPI] +4000h [31]) to be set back to 0 >=20 > + // 4. Check the transaction status in SCRS (bits [30:28]) >=20 > + // >=20 > + return EspiSlaveOperationHelper (SlaveId, 0, > EspiSlaveOperationInBandReset, NULL); >=20 > +} >=20 > + >=20 > +/** >=20 > + eSPI Slave channel reset helper function >=20 > + >=20 > + @param[in] SlaveId eSPI slave ID >=20 > + @param[in] ChannelNumber Number of channel to reset >=20 > + >=20 > + @retval EFI_SUCCESS Operation succeeded >=20 > + @retval EFI_UNSUPPORTED Slave doesn't support that channel or > invalid number specified >=20 > + @retval EFI_TIMEOUT Operation has timeouted >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchEspiSlaveChannelReset ( >=20 > + IN UINT8 SlaveId, >=20 > + IN UINT8 ChannelNumber >=20 > + ) >=20 > +{ >=20 > + UINT8 Timeout; >=20 > + UINT32 Data32; >=20 > + UINT32 SlaveChannelAddress; >=20 > + BOOLEAN SlaveBmeSet; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "eSPI slave %d channel %d reset\n", SlaveId, > ChannelNumber)); >=20 > + >=20 > + Timeout =3D CHANNEL_RESET_TIMEOUT; >=20 > + SlaveBmeSet =3D FALSE; >=20 > + >=20 > + if (!IsEspiSlaveChannelSupported (SlaveId, ChannelNumber)) { >=20 > + // Incorrect channel number was specified. Either exceeded max or Sl= ave > doesn't support that channel. >=20 > + DEBUG ((DEBUG_ERROR, "Channel %d is not valid channel number for > slave %d!\n", ChannelNumber, SlaveId)); >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + // Calculating slave channel address >=20 > + SlaveChannelAddress =3D R_ESPI_SLAVE_CHACAP_BASE + > (S_ESPI_SLAVE_CHACAP_OFFSET * ChannelNumber); >=20 > + >=20 > + // If we're resetting Peripheral Channel then we need to disable Bus > Mastering first and reenable after reset >=20 > + if (ChannelNumber =3D=3D 0) { >=20 > + PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data32); >=20 > + if ((Data32 & B_ESPI_SLAVE_BME) !=3D 0) { >=20 > + Data32 &=3D ~(B_ESPI_SLAVE_BME); >=20 > + PchEspiSlaveSetConfig (SlaveId, SlaveChannelAddress, Data32); >=20 > + SlaveBmeSet =3D TRUE; >=20 > + } >=20 > + } >=20 > + >=20 > + // Disable channel >=20 > + PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data32); >=20 > + Data32 &=3D ~(B_ESPI_SLAVE_CHACAP_CHEN); >=20 > + PchEspiSlaveSetConfig (SlaveId, SlaveChannelAddress, Data32); >=20 > + >=20 > + // Enable channel >=20 > + PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data32); >=20 > + Data32 |=3D B_ESPI_SLAVE_CHACAP_CHEN; >=20 > + PchEspiSlaveSetConfig (SlaveId, SlaveChannelAddress, Data32); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "Waiting for Channel Ready bit\n")); >=20 > + // Wait until channel is ready by polling Channel Ready bit >=20 > + while (((Data32 & B_ESPI_SLAVE_CHACAP_CHRDY) =3D=3D 0) && (Timeout > > 0)) { >=20 > + PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data32); >=20 > + MicroSecondDelay (1); >=20 > + --Timeout; >=20 > + } >=20 > + >=20 > + if (Timeout =3D=3D 0) { >=20 > + // The waiting for channel to be ready has timed out >=20 > + DEBUG ((DEBUG_ERROR, "The operation of channel %d reset for slave %d > has timed out!\n", ChannelNumber, SlaveId)); >=20 > + return EFI_TIMEOUT; >=20 > + } >=20 > + >=20 > + if (ChannelNumber =3D=3D 0 && SlaveBmeSet) { >=20 > + PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data32); >=20 > + Data32 |=3D B_ESPI_SLAVE_BME; >=20 > + PchEspiSlaveSetConfig (SlaveId, SlaveChannelAddress, Data32); >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib= /P > eiDxeSmmEspiLib.inf > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib= /P > eiDxeSmmEspiLib.inf > new file mode 100644 > index 0000000000..440051432f > --- /dev/null > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib= /P > eiDxeSmmEspiLib.inf > @@ -0,0 +1,38 @@ > +## @file >=20 > +# Component description file for the PeiDxeSmmPchEspiLib >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > + >=20 > +[Defines] >=20 > +INF_VERSION =3D 0x00010017 >=20 > +BASE_NAME =3D PeiDxeSmmEspiLib >=20 > +FILE_GUID =3D 7F25F990-7989-4413-B414-1EDE557E9389 >=20 > +VERSION_STRING =3D 1.0 >=20 > +MODULE_TYPE =3D BASE >=20 > +LIBRARY_CLASS =3D EspiLib >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC >=20 > +# >=20 > + >=20 > + >=20 > + >=20 > +[LibraryClasses] >=20 > +BaseLib >=20 > +IoLib >=20 > +DebugLib >=20 > +PchPcrLib >=20 > +TimerLib >=20 > + >=20 > +[Packages] >=20 > +MdePkg/MdePkg.dec >=20 > +TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > + >=20 > +[Sources] >=20 > +EspiLib.c >=20 > -- > 2.24.0.windows.2